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부품번호 | IDT709169 기능 |
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기능 | HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | ||
제조업체 | IDT | ||
로고 | |||
HIGH-SPEED 16/8K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT709169/59L
Features
◆ True Dual-Ported memory cells which allow simultaneous
access of the same memory location
◆ High-speed clock to data access
– Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
◆ Low-power operation
– IDT709169/59L
Active: 925mW (typ.)
Standby: 2.5mW (typ.)
◆ Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
◆ Counter enable and reset features
◆ Dual chip enables allow for depth expansion without
additional logic
Functional Block Diagram
◆ Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time,100MHz operation in Pipelined output mode
◆ TTL- compatible, single 5V (±10%) power supply
◆ Industrial temperature range (–40°C to +85°C) is
available for 83MHz
◆ Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin fine pitch Ball Grid Array (fpBGA) packages.
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
A13L(1)
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
NOTE:
1. A13 is a NC for IDT709159.
FT/PIPER
I/O0R - I/O8R
A13R(1)
A0R
CLKR
ADSR
CNTENR
CNTRSTR
5653 drw 01
©2009 Integrated Device Technology, Inc.
1
JANUARY 2009
DSC-5653/3
IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
Pin Names
Left Port
CE0L, CE1L
R/WL
OEL
A0L - A13L(1)
I/O0L - I/O8L
CLKL
ADSL
CNTENL
CNTRSTL
FT/PIPEL
Right Port
CE0R, CE1R
R/WR
OER
A0R - A13R(1)
I/O0R - I/O8R
CLKR
ADSR
CNTENR
CNTRSTR
FT/PIPER
VCC
GND
NOTE:
1. A13 is a NC for IDT709159.
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (5V)
Ground (0V)
5653 tbl 01
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-8
Mode
X↑HXX
High-Z Deselected—Power Down
X↑X LX
High-Z Deselected—Power Down
X↑ L HL
DATAIN Write
L ↑ L H H DATAOUT Read
HX L HX
High-Z Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
5653 tbl 02
6.442
4페이지 IDT709169/59L
High-Speed 16/8K x 9 Synchronous Pipelined Dual-Port Static RAM
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
GND to 3.0V
2ns Max.
1.5V
Output Reference Levels
Output Load
1.5V
Figures 1, 2 and 3
5653 tbl 10
Industrial and Commercial Temperature Ranges
DATAOUT
347Ω
5V
893Ω
30pF
DATAOUT
347Ω
5V
893Ω
5pF*
5653 drw 04
Figure 1. AC Output Test load.
5653 drw 05
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
tCD1,
tCD2
(Typical, ns)
8
7
6
5
4
3
2
1
0
-1
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
5653 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.742
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
IDT709169 | HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | IDT |
IDT709169L | HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |