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IDT70T3399S PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 IDT70T3399S
기능 HIGH-SPEED 2.5V 512/256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM
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IDT70T3399S 데이터시트, 핀배열, 회로
HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UBL
LBL
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
ab
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Dout9-17_R
1b 0b
b
1a 0a
a
1/0
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
512/256/128K x 18
MEMORY
ARRAY
0a 1a 0b
1b
ba
0/1
FT/PIPER
,
I/O0L - I/O17L
Din_L
Din_R
I/O0R - I/O17R
CLKL
A18L(1)
A0L
REPEATL
ADSL
CNTENL
COL L
INTL
Counter/
Address
Reg.
CE 0 L
CE 1L
R/W L
ADDR_L
ADDR_R
INTERRUPT
COLLISION
DETECTION
LOGIC
ZZL(2)
ZZ
CO NTRO L
LOGIC
Counter/
Address
Reg.
R/WR
CE0 R
CE1R
ZZR(2)
CLKR
A18R(1)
A0R
REPEATR
ADSR
CNTENR
TDI
TDO
COLR
INTR
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2015 Integrated Device Technology, Inc.
1
,
TCK
JTAG TMS
TRST
5652 drw 01
JUNE 2015
DSC-5652/8




IDT70T3399S pdf, 반도체, 판매, 대치품
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Pin Configurations(con't)(3,4,5,6,9)
Industrial and Commercial Temperature Ranges
12 3 4 56 7 8
I/O9L INTL VSS TDO NC A16L
A12L A8L
9 10 11 12 13 14 15 16 17
NC VDD CLKL CNTEN L A4L
A0L OPT L NC VSS
A
BNC VSS COLL TDI A17L(2) A13L A9L NC CE0L VSS ADSL A5L A1L NC VDDQR I/O8L NC
VDDQL I/O9R VDDQR PIPE/FTL A18L(1) A14L A10L
UBL CE1L
VSS R/WL
A6L
CA2L VDD I/O8R NC VSS
DNC
VSS I/O10L NC
A15L A11L
A7L
LBL VDD OEL REPEATL A3L VDD
NC VDDQL I/O7L I/O7R
I/O11L NC VDDQR I/O10R
I/O6L NC
VSS NC
E
VDDQL I/O11R NC
VSS
FVSS I/O6R NC VDDQR
NC VSS I/O12L NC
GNC VDDQL I/O5L NC
VDD NC VDDQR I/O12R
VDDQL VDD VSS ZZR
I/O14R VSS I/O13R VSS
NC I/O14L VDDQR I/O13L
70T3339/19/99BF
BF-208(7)
208-Pin fpBGA
Top View(8)
HVDD NC
VSS I/O5R
JZZL VDD VSS VDDQR
I/O3R VDDQL I/O4R VSS
K
LNC I/O3L VSS I/O4L
VDDQL NC I/O15R VSS
MVSS NC I/O2R VDDQR
NC VSS NC I/O15L
NI/O1R VDDQL NC I/O2L
I/O16R I/O16L VDDQR COLR TRST A16R A12R A8R NC
VDD CLKR CNTEN R A4R NC
I/O1L VSS
NC P
RVSS NC I/O17R TCK A17R(2) A13R A9R NC CE0R VSS ADSR A5R A1R NC VDDQL I/O0R VDDQR
TNC I/O17L VDDQL TMS A18R(1) A14R A10R UBR CE1R VSS R/WR A6R A2R VSS NC VSS NC
UVSS INTR PIPE/FTR NC
A15R A11R
A7R
LBR
VDD
OER REPEATR A3R
A0R
VDD OPT R NC I/O0L
5652 drw 02c
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
6.42

4페이지










IDT70T3399S 전자부품, 판매, 대치품
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Maximum Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature
GND
VDD
Commercial
0OC to +70OC
0V 2.5V + 100mV
Industrial
-40OC to +85OC 0V 2.5V + 100mV
NOTE:
5652 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Min. Typ.
Max.
Unit
VDD Core Supply Voltage
2.4 2.5
2.6
V
VDDQ I/O Supply Voltage(3)
2.4 2.5
2.6
V
VSS Ground
00 0 V
Input High Volltage
VIH (Address, Control &
Data I/O Inputs)(3)
1.7
____ VDDQ + 100mV(2)
V
VIH
Input High Voltage _
JTAG
1.7
____ VDD + 100mV(2)
V
VIH
Input High Voltage -
ZZ, OPT, PIPE/FT
VDD - 0.2V ____ VDD + 100mV(2)
V
VIL Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
NOTES:
5652 tbl 05a
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as
indicated above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD Core Supply Voltage
2.4 2.5
2.6
V
VDDQ I/O Supply Voltage(3)
3.15 3.3
3.45
V
VSS Ground
00 0 V
Input High Voltage
VIH (Address, Control
&Data I/O Inputs)(3)
2.0 ____ VDDQ + 150mV(2) V
VIH
Input High Voltage _
JTAG
1.7
____ VDD + 100mV(2)
V
VIH
Input High Voltage -
ZZ, OPT, PIPE/FT
VDD - 0.2V ____ VDD + 100mV(2) V
VIL Input Low Voltage
-0.3(1)
____
0.8
V
VIL
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
____
0.2
V
NOTES:
5652 tbl 05b
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied
as indicated above.
6.742

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