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IDT70T3799M 데이터시트 PDF




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부품번호 IDT70T3799M 기능
기능 HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM
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IDT70T3799M 데이터시트, 핀배열, 회로
HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
IDT70T3719/99M
Š DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
Green parts available, see ordering information
Functional Block Diagram
BE7L
BE7R
BE0L
BE0R
FT/PIP EL
0a 1a
1/0
a
0h 1h
h
1h 0h
h
1a 0a
1/0
a
FT/PIPER
R/WL
R/WR
CE0L
CE1L
OEL
FT/PIPEL
1
0
1/0
1h 0h
0/1
a
1a 0a
h
Byte 0
I/O0L - I/O71L
CLKL
A17L(1)
A 0L
REPEATL
ADSL
CN TENL
Byte 7
Counter/
Address
Reg.
B
BB
B
W
WW
W
0
77
0
L
LR
R
D OUT0-8_ L
D OUT9-17 _L
DO UT18-26_L
D OUT 27-3 5_ L
D OUT 36-4 4_L
D OUT 45-5 3_L
D OUT 54-6 2_L
D OUT 63-7 2_L
D OUT0-8_ R
D OUT9-17 _R
D OU T1 8-2 6_ R
DOUT27 -35_ R
DOUT36 -4 4_ R
DOUT45 -5 3_ R
DOUT54 -6 2_ R
DOUT63 -7 2_ R
256/128K x 72
MEM ORY
ARRAY
DIN_L
DIN_R
ADDR_L
ADDR_R
0a 1a
h
0h 1h
a
0/1
Byte 7
Counter/
Address
Reg.
Byte 0
I/O0R - I/O71R
A17R(1)
CLKR
A 0R
REPE ATR
AD SR
CNTENR
COL L
INTL
CE0L
CE1L
R/WL
INTERRUPT
COLLISION
DETECTION
LOGIC
CE0R
CE1R
R/WR
COL R
INTR
NOTES:
ZZ
(2)
L
ZZ
CONTROL
LOGIC
ZZ
(2)
R
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
©2014 Integrated Device Technology, Inc.
TDI
T DO
C E0 R
1 CE1R
0
1/0
OER
FT/PIPER
,
,
JTAG
TC K
TMS
TRST
5687 drw 01
JULY 2014
DSC 5687/3




IDT70T3799M pdf, 반도체, 판매, 대치품
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A17L(5)
OER
A0R - A17R(5)
I/O0L - I/O71L
I/O0R - I/O71R
CLKL
CLKR
PL/FTL
PL/FTR
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
BE0L - BE7L
VDDQL
OPTL
BE0R - BE7R
VDDQR
OPTR
ZZL ZZR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
INTL
COLL
INTR
COLR
Names
Chip Enables (Input)(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
Byte Enables (9-bit bytes) (Input)(6)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
5687 tbl 02
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A17x is a NC for the IDT70T3799M.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.442

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IDT70T3799M 전자부품, 판매, 대치품
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM
(VDD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
V
VTERM(2)
(VDDQ)
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
TBIAS(3)
Temperature Under Bias
-55 to +125
oC
TSTG
Storage Temperature
-65 to +150
oC
TJN
Junction Temperature
+150
oC
IOUT(For VDDQ = 3.3V) DC Output Current
50 mA
IOUT(For VDDQ = 2.5V) DC Output Current
40 mA
NOTES:
5687 tbl 07
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance (1)
(TA = +25°C, F = 1.0MHZ)
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
VIN = 0V
15 pF
COUT(2) Output Capacitance
VOUT = 0V
10.5 pF
5687 tbl 08
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. COUT also references CI/O.
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
Symbol
|ILI|
|ILI|
|ILO|
VOL (3.3V)
VOH (3.3V)
VOL (2.5V)
VOH (2.5V)
Parameter
Input Leakage Current(1)
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
Output Low Voltage(1)
Output High Voltage(1)
Output Low Voltage(1)
Output High Voltage(1)
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
VDD = Max., VIN = 0V to VDD
CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
IOL = +4mA, VDDQ = Min.
IOH = -4mA, VDDQ = Min.
IOL = +2mA, VDDQ = Min.
IOH = -2mA, VDDQ = Min.
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
70T3719/99M
Min. Max.
___ 10
___ ±30
___ 10
___ 0.4
2.4 ___
___ 0.4
2.0 ___
Unit
µA
µA
µA
V
V
V
V
5687 tbl 09
6.472

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부품번호상세설명 및 기능제조사
IDT70T3799

HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT
IDT
IDT70T3799M

HIGH-SPEED 2.5V 256/128K x 72 SYNCHRONOUS DUAL-PORT STATIC RAM

IDT
IDT

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