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PDF IDT70V7599S Data sheet ( Hoja de datos )
| Número de pieza | IDT70V7599S | |
| Descripción | HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM | |
| Fabricantes | IDT | |
| Logotipo |  |
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HIGH-SPEED 3.3V 128K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7599S
Features:
◆ 128K x 36 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
– 64 independent 2K x 36 banks
– 4 megabits of memory on chip
◆ Bank access controlled via bank address pins
◆ High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
◆ Selectable Pipelined or Flow-Through output mode
◆ Counter enable and repeat features
◆ Dual chip enables allow for depth expansion without
additional logic
◆ Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ LVTTL- compatible, 3.3V (±150mV) power supply
for core
◆ LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV)
power supply for I/Os and control signals on each port
◆ Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
◆ Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
◆ Supports JTAG features compliant with IEEE 1149.1
◆ Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A10L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2015 Integrated Device Technology, Inc.
MUX
2Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 1)
MUX
MUX
2Kx36
MEMORY
ARRAY
(BANK 63)
MUX
TDI
TDO
JTAG
1
TMS
TCK
TRST
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A10R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5626 drw 01
,
JUNE 2015
DSC 5626/7
1 page  
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
BA0L - BA5L
A0L - A10L
I/O0L - I/O35L
CLKL
OER
BA0R - BA5R
A0R - A10R
I/O0R - I/O35R
CLKR
PL/FTL
PL/FTR
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
BE0L - BE3L
VDDQL
OPTL
BE0R - BE3R
VDDQR
OPTR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
Names
Chip Enables
Read/Write Enable
Output Enable
Bank Address(4)
Address
Data Input/Output
Clock
Pipeline/Flow-Through
Address Strobe Enable
Counter Enable
Counter Repeat(3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
Option for selecting VDDQX(1,2)
Power (3.3V)(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5626 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
6.452
5 Page 
IDT70V7599S
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V7599S200(5)
Com'l Only
70V7599S166(3,4)
Com'l
& Ind
70V7599S133(3)
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tCYC1 Clock Cycle Time (Flow-Through)(1)
15 ____ 20 ____ 25 ____ ns
tCYC2 Clock Cycle Time (Pipelined)(1)
5 ____ 6 ____ 7.5 ____ ns
tCH1 Clock High Time (Flow-Through)(1)
5 ____ 6 ____ 7 ____ ns
tCL1 Clock Low Time (Flow-Through)(1)
5 ____ 6 ____ 7 ____ ns
tCH2 Clock High Time (Pipelined)(2)
2.0 ____ 2.1 ____ 2.6 ____ ns
tCL2 Clock Low Time (Pipelined)(1)
2.0 ____ 2.1 ____ 2.6 ____ ns
tR Clock Rise Time
____ 1.5 ____ 1.5 ____ 1.5 ns
tF Clock Fall Time
____ 1.5 ____ 1.5 ____ 1.5 ns
tSA Address Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHA Address Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSC Chip Enable Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHC Chip Enable Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSB Byte Enable Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHB Byte Enable Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSW R/W Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHW R/W Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSD Input Data Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHD Input Data Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSAD ADS Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHAD ADS Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSCN CNTEN Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHCN CNTEN Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSRPT REPEAT Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHRPT REPEAT Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tOE Output Enable to Data Valid
____ 4.0 ____ 4.0 ____ 4.2 ns
tOLZ Output Enable to Output Low-Z
0.5 ____ 0.5 ____ 0.5 ____ ns
tOHZ Output Enable to Output High-Z
1 3.4 1 3.6 1 4.2 ns
tCD1 Clock to Data Valid (Flow-Through)(1)
____ 10 ____ 12 ____ 15 ns
tCD2 Clock to Data Valid (Pipelined)(1)
____ 3.4 ____ 3.6 ____ 4.2 ns
tDC Data Output Hold After Clock High
1 ____
1 ____
1 ____ ns
tCKHZ Clock High to Output High-Z
1 3.4 1 3.6 1 4.2 ns
tCKLZ Clock High to Output Low-Z
0.5 ____ 0.5 ____ 0.5 ____ ns
Port-to-Port Delay
tCO Clock-to-Clock Offset
5.0 ____ 6.0 ____ 7.5 ____ ns
NOTES:
5626 tbl 11
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPEX = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
4. 166MHz Industrial Temperature not available in BF-208 package.
5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC256 package only.
6.1412
11 Page | ||
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| PDF Descargar | [ Datasheet IDT70V7599S.PDF ] | |
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