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IDT70V9199L PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 IDT70V9199L
기능 HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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IDT70V9199L 데이터시트 및 IDT70V9199L PDF

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IDT70V9199L pdf, 반도체, 판매, 대치품
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A16L
I/O0L - I/O8L(1)
OER
A0R - A16R
I/O0R - I/O8R(1)
CLKL
CLKR
ADSL
ADSR
CNTENL
CNTENR
CNTRSTL
CNTRSTR
FT/PIPEL
FT/PIPER
VDD
VSS
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
4859 tbl 01
NOTE:
1. I/O0X - I/O7X for IDT70V9099.
Truth Table I—Read/Write and Enable Control(1,2,3)
OE CLK CE0 CE1 R/W
I/O0-8(4)
X HX X
High-Z
Deselected–Power Down
XX LX
High-Z
Deselected–Power Down
XL HL
DATAIN
Write
LL HH
DATAOUT
Read
HX L HX
High-Z
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. I/O0 - I/O7 for IDT70V9099.
MODE
4859 tbl 02
Truth Table II—Address Counter Control(1,2)
Previous Internal
External Internal Address
Address Address
Used
CLK ADS CNTEN CNTRST
I/O(3)
MODE
X
X
0
X
X
L(4) DI/O(0) Counter Reset to Address 0
An X An L(4) X H DI/O(n) External Address Loaded into Counter
An Ap
Ap H H
H DI/O(p) External Address Blocked—Counter disabled (Ap reused)
X
Ap
Ap + 1
H
L(5)
H DI/O(p+1) Counter Enabled—Internal Address generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
4859 tbl 03
6.442

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IDT70V9199L 전자부품, 판매, 대치품
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
AC Test Conditions
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1, 2, and 3
4859 tbl 10
Industrial and Commercial Temperature Ranges
DATAOUT
435
3.3V
590
30pF
DATAOUT
435
3.3V
590
5pF*
4859 drw 03
Figure 1. AC Output Test load.
4859 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
tCD1,
tCD2
(Typical, ns)
8
7
6
5
4
3
2
1
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
0
20 40 60 80 100 120 140 160 180 200
-1 Capacitance (pF)
.
4859 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.472

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