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IDT70V9289 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 IDT70V9289
기능 HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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IDT70V9289 데이터시트, 핀배열, 회로
HIGH-SPEED 3.3V
64K x18/x16
SYNCHRONOUS PIPELINED IDT70V9389/289L
Š DUAL-PORT STATIC RAM
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9389/289L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
LVTTL- compatible, single 3.3V (±0.3V) power supply
Functional Block Diagram
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output
mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Flatpack (TQFP) and
100-pin Thin Quad Flatpack (TQFP)
Green parts available, see ordering information
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
FT/PIPEL
I/O9L-I/O17L(2)
I/O0L-I/O8L(1)
A15L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
0/1 1b 0b b a 1a 0a
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
FT/PIPER
I/O9R-I/O17R(1)
I/O0R-I/O8R(1)
A15R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4856 drw 01
NOTES:
1. I/O0X - I/O7X for IDT70V9289.
2. I/O8X - I/O15X for IDT70V9289.
©2014 Integrated Device Technology, Inc.
1
MARCH 2014
DSC-4856/8




IDT70V9289 pdf, 반도체, 판매, 대치품
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Pin Configurations(1,2,3)(con't.)
Industrial & Commercial Temperature Ranges
02/25/14
NC
NC
NC
NC
A9R
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
VSS
VDD
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V9289PRF
PK128(4)
128-Pin TQFP
Top View(5)
102 I/O10R
101 I/O9R
100 VSS
99 NC
98 I/O8R
97 NC
96 NC
95 I/O7R
94 VDD
93 I/O6R
92 I/O5R
91 I/O4R
90 VSS
89 I/O3R
88 VDD
87 I/O2R
86 I/O1R
85 I/O0R
84 VSS
83 VDD
82 I/O0L
81 I/O1L
80 VSS
79 I/O2L
78 I/O3L
77 VSS
76 I/O4L
75 I/O5L
74 I/O6L
73 I/O7L
72 VDD
71 NC
70 NC
69 I/O8L
68 NC
67 VDD
66 I/O9L
65 I/O10L
4856 drw 02b
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.442

4페이지










IDT70V9289 전자부품, 판매, 대치품
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous Internal
External Internal Address
Address Address Used CLK ADS CNTEN CNTRST
I/O(3)
MODE
X
X
0 X
X
L(4) DI/O(0) Counter Reset to Address 0
An X An L(4) X H DI/O(n) External Address Loaded into Counter
An Ap Ap H H
H DI/O(p) External Address Blocked—Counter disabled (Ap reused)
X
Ap Ap + 1
H
L(5)
H DI/O(p+1) Counter Enabled—Internal Address generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
4856 tbl 03
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature(2)
GND
VDD
Commercial
0OC to +70OC 0V 3.3V + 0.3V
Industrial
-40OC to +85OC
0V
3.3V + 0.3V
NOTE:
4856 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD Supply Voltage
3.0 3.3 3.6 V
VSS Ground
00
0V
VIH Input High Voltage
2.0 ____ VDD+0.3V(2) V
VIL Input Low Voltage
-0.3(1)
____
0.8
V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
4856 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS(3)
Temperature
Under Bias
-55 to +125
oC
TSTG
Storage
Temperature
-65 to +150
oC
TJN Junction Temperature
+150
oC
IOUT DC Output Current
50 mA
NOTES:
4856 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Parameter
Conditions(2) Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT(3) Output Capacitance
VOUT = 3dV
10 pF
NOTES:
4856 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
6.472

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