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PDF PIC24FJ64GA310 Data sheet ( Hoja de datos )
| Número de pieza | PIC24FJ64GA310 | |
| Descripción | 16-Bit Flash Microcontrollers | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PIC24FJ128GA310 FAMILY
64/80/100-Pin, General Purpose, 16-Bit Flash Microcontrollers
with LCD Controller and nanoWatt XLP Technology
Extreme Low-Power Features:
• Multiple Power Management Options for Extreme
Power Reduction:
- VBAT allows the device to transition to a back-up
battery for the lowest power consumption with
RTCC
- Deep Sleep allows near total power-down, with
the ability to wake-up on external triggers
- Sleep and Idle modes selectively shut down
peripherals and/or core for substantial power
reduction and fast wake-up
- Doze mode allows CPU to run at a lower clock
speed than peripherals
• Alternate Clock modes Allow On-the-Fly Switching to
a Lower Clock Speed for Selective Power Reduction
• Extreme Low-Power Current Consumption for
Deep Sleep:
- WDT: 270 nA @ 3.3V typical
- RTCC: 400 nA @ 32 kHz, 3.3V typical
- Deep Sleep current, 40 na, 3.3V typical
Peripheral Features:
• LCD Display Controller:
- Up to 60 segments by 8 commons
- Internal charge pump and low-power, internal
resistor biasing
- Operation in Sleep mode
• Up to Five External Interrupt Sources
• Peripheral Pin Select (PPS): Allows Independent I/O
Mapping of Many Peripherals
• Five 16-Bit Timers/Counters with Prescaler:
- Can be paired as 32-bit timers/counters
• Six-Channel DMA supports All Peripheral modules
- Minimizes CPU overhead and increases data
throughput
Peripheral Features (continued):
• Seven Input Capture modules, each with a
Dedicated 16-Bit Timer
• Seven Output Compare/PWM modules, each with a
Dedicated 16-Bit Timer
• Enhanced Parallel Master/Slave Port (EPMP/EPSP)
• Hardware Real-Time Clock/Calendar (RTCC):
- Runs in Deep Sleep and VBAT modes
• Two 3-Wire/4-Wire SPI modules (support 4 Frame
modes) with 8-Level FIFO Buffer
• Two I2C™ modules Support Multi-Master/Slave
mode and 7-Bit/10-Bit Addressing
• Four UART modules:
- Support RS-485, RS-232 and LIN/J2602
- On-chip hardware encoder/decoder for IrDA®
- Auto-wake-up on Auto-Baud Detect
- 4-level deep FIFO buffer
• Programmable 32-bit Cyclic Redundancy Check
(CRC) Generator
• Digital Signal Modulator Providers On-Chip FSK and
PSK Modulation for a Digital Signal Stream
• Configurable Open-Drain Outputs on Digital I/O Pins
• High-Current Sink/Source (18 mA/18 mA) on All I/O Pins
Analog Features:
• 10/12-Bit, 24-Channel Analog-to-Digital (A/D) Converter:
- Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
- Conversion available during Sleep and Idle
• Three Rail-to-Rail Enhanced Analog Comparators
with Programmable Input/Output Configuration
• On-Chip Programmable Voltage Reference
• Charge Time Measurement Unit (CTMU):
- Used for capacitive touch sensing, up to 24 channels
- Time measurement down to 1 ns resolution
- CTMU temperature sensing
Memory
Remappable Peripherals
Device
PIC24FJ128GA310 100 128K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y
PIC24FJ128GA308
80 128K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y
PIC24FJ128GA306
64 128K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y
PIC24FJ64GA310
100 64K 8K 5 7 7 4 2 2 24 3 24 Y 480 Y Y
PIC24FJ64GA308
80 64K 8K 5 7 7 4 2 2 16 3 16 Y 368 Y Y
PIC24FJ64GA306
64 64K 8K 5 7 7 4 2 2 16 3 16 Y 240 Y Y
2010-2011 Microchip Technology Inc.
DS39996F-page 1
1 page  
Pin Diagrams (continued)
PIC24FJ128GA310 FAMILY
100-Pin TQFP
SEG51/CTED3/CN82/RG15
VDD
CTED4/PMD5/LCDBIAS2/CN63/RE5
PMD6/LCDBIAS1/CN64/RE6
PMD7/LCDBIAS0/CN65/RE7
RPI38/SEG32/CN45/RC1
RPI39/SEG52/CN46/RC2
RPI40/SEG33/CN47/RC3
AN16/RPI41/SEG53/PMCS2/CN48/RC4
AN17/C1IND/RP21/SEG0/PMA5/CN8/RG6
VLCAP1/AN18/C1INC/RP26/PMA4/CN9/RG7
VLCAP2/AN19/C2IND/RP19/PMA3/CN10/RG8
MCLR
AN20/C2INC/RP27/SEG1/PMA2/CN11/RG9
VSS
VDD
TMS/CTED0/SEG49/CN33/RA0
RPI33/SEG34/PMCS1/CN66/RE8
AN21/RPI34/SEG35/PMA19/CN67/RE9
PGEC3/AN5/C1INA/RP18/SEG2/CN7/RB5
PGED3/AN4/C1INB/RP28/SEG3/CN6/RB4
AN3/C2INA/SEG4/CN5/RB3
AN2/C2INB/RP13/SEG5/CTED13/CTCMP/CN4/RB2
PGEC1/CVREF-/AN1/RP1/SEG6/CTED12/CN3/RB1
PGED1/CVREF+/AN0/RP0/SEG7/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC24FJXXXGA310
75 VSS
74 RPI37/SOSCO/SCLKI/RC14
73 SOSCI/RC13
72 RP11/SEG17/CN49/RD0
71 RP12/SEG16/C3INC/PMA14/CS1/CN56/RD11
70 RP3/SEG15/C3IND/PMA15/CS2/CN55/RD10
69 RP4/SEG14/PMACK2/CN54/RD9
68 RP2/SEG13/RTCC/CN53/RD8
67 RPI35/SEG43/PMBE1/CN44/RA15
66 RPI36/SEG42/PMA22/CN43/RA14
65 VSS
64 OSCO/CLKO/CN22/RC15
63 OSCI/CLKI/CN23/RC12
62 VDD
61 TDO/CN38/RA5
60 TDI/PMA21/CN37/RA4
59 SDA2/SEG57/PMA20/CN36/RA3
58 SCL2/SEG56/CN35/RA2
57 SCL1/SEG28/CN72/RG2
56 SDA1/SEG47/CN73/RG3
55 INT0/CN84/RF6
54 CN83/RF7
53 RP15/SEG41/CN74/RF8
52 RP30/SEG40/CN70/RF2
51 RP16/SEG12/CN71/RF3
Legend:
Note:
RPn and RPIn represent remappable pins for Peripheral Pin Select feature. Shaded pins indicate pins that are tolerant up to +5.5V.
Pinouts are subject to change.
2010-2011 Microchip Technology Inc.
DS39996F-page 5
5 Page 
PIC24FJ128GA310 FAMILY
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
• PIC24FJ64GA306
• PIC24FJ64GA308
• PIC24FJ64GA310
• PIC24FJ128GA306
• PIC24FJ128GA308
• PIC24FJ128GA310
The PIC24FJ128GA310 family adds many new fea-
tures to Microchip‘s 16-bit microcontrollers, including
new ultra low-power features, Direct Memory Access
(DMA) for peripherals, and a built-in LCD Controller
and Driver. Together, these provide a wide range of
powerful features in one economical and power-saving
package.
1.1 Core Features
1.1.1 16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC® Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such
as:
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2
nanoWatt XLP POWER-SAVING
TECHNOLOGY
The PIC24FJ128GA310 family of devices introduces a
greatly-expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep, with essential circuits being
powered from a separate low-voltage regulator
• Deep Sleep without RTCC, for the lowest possible
power consumption under software control
• VBAT mode (with or without RTCC), to continue
operation limited operation from a back-up battery
when VDD is removed
Many of these new low-power modes also support the
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
Aside from these new features, PIC24FJ128GA310 fam-
ily devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower-power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of Idle and the many Sleep modes.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
All of the devices in the PIC24FJ128GA310 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
• A Fast Internal Oscillator (FRC) (nominal 8 MHz
output) with multiple frequency divider options
• A separate Low-Power Internal RC Oscillator
(LPRC) (31 kHz nominal) for low-power,
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4 EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. The
consistent pinout scheme used throughout the entire
family also aids in migrating from one device to the next
larger, or even in jumping from 64-pin to 100-pin
devices.
The PIC24F family is pin compatible with devices in the
dsPIC33 family, and shares some compatibility with the
pinout schema for PIC18 and dsPIC30. This extends
the ability of applications to grow from the relatively
simple, to the powerful and complex, yet still selecting
a Microchip device.
2010-2011 Microchip Technology Inc.
DS39996F-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC24FJ64GA310.PDF ] | |
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