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PDF ISP12160 Data sheet ( Hoja de datos )
| Número de pieza | ISP12160 | |
| Descripción | Dual SCSI Processor | |
| Fabricantes | QLogic | |
| Logotipo |  |
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QLogic Corporation
ISP12160 Intelligent, Dual SCSI Processor
Data Sheet
Features
s 33-MHz, 64-bit PCI host bus interface
(ISP12160/33), compliant with PCI Local Bus
Specification rev 2.1
s Compliance with ANSI draft T10/1302D SCSI-3
Parallel Interface (SPI-3)
s Supports Ultra160/m SCSI
s SCSI feature set: dual transition, cyclical
redundancy check (CRC), domain validation
s Compliance with PCI Bus Power Management
Interface Specification Revision 1.0 (PC98)
s Two concurrently operating wide, Ultra160/m SCSI
channels
s Up to 160 Mbytes/sec parallel SCSI transfer rates
per channel
s Supports single-ended, low voltage differential
(LVD) SCSI
s SCSI initiator and target modes of operation
s Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
s Supports PCI dual-address cycle (64-bit
addressing)
s No host intervention required to execute SCSI
operations from start to finish
s Simultaneous, multiple logical threads
s JTAG boundary scan support
Product Description
The ISP12160 supports dual channel, Ultra160/m
(Fast-80) SCSI functionality and is pin compatible with
QLogic’s ISP1280 Ultra2 SCSI processor. The product is
a single-chip, highly integrated bus master, dual-channel
SCSI I/O processor for SCSI initiator and target
applications. This device interfaces the PCI bus to two
Ultra160/m SCSI buses and contains an onboard RISC
processor. The product is a fully autonomous device,
capable of managing multiple I/O operations and
associated data transfers from start to finish without host
intervention. The ISP12160 provides power management
feature support in accordance with the PCI Bus Power
Management Interface Specification. The ISP12160 is
host-software compatible with the QLogic ISP1280 chip.
The ISP12160 block diagram is illustrated in figure 1.
ISP Initiator and Target Firmware
The ISP12160 firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery, while the multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP12160 can switch between initiator and target modes.
Software Drivers
Software drivers are available for all major operating
systems. ISP12160 BIOS firmware is also available.
Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP12160 incorporates a
high-speed proprietary RISC processor; an intelligent
SCSI bus controller (SCSI executive processor [SXP]); and
a host bus, dual-channel DMA controller. The SCSI bus
controller and the host bus DMA controller operate
independently and concurrently under the control of the
onboard RISC processor for maximum system
performance. The ISP12160 RISC interface requires
external program and data memory.
The complete I/O subsystem solution including the
ISP12160 and associated supporting memory devices is
shown in figure 2.
83216-580-00 C
ISP12160
1
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| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet ISP12160.PDF ] | |
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