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ADM1278 데이터시트 PDF




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부품번호 ADM1278 기능
기능 Hot Swap Controller and Digital Power and Energy Monitor
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ADM1278 데이터시트, 핀배열, 회로
Data Sheet
Hot Swap Controller and Digital Power and
Energy Monitor with PMBus Interface
ADM1278
FEATURES
±0.3% accurate, 12-bit ADC for IOUT, VIN, VOUT, and temperature
320 ns response time to short circuit
Shutdown on detection of FET health fault
Constant power foldback for tighter FET SOA protection
Remote temperature sensing with programmable warning
and shutdown thresholds
Resistor-programmable 5 mV to 25 mV VSENSE current limit
Programmable start-up current limit
1% accurate UV, OV, and PWRGD thresholds
Split hot swap and power monitor inputs to allow additional
external ADC filtering
Reports power and energy consumption over time
Peak detect registers for current, voltage, and power
PROCHOT power throttling capability
PMBus fast mode compliant interface
5 mm × 5 mm, 32-lead LFCSP
APPLICATIONS
Servers
Power monitoring and control/power budgeting
Telecommunication and data communication equipment
GENERAL DESCRIPTION
The ADM1278 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current, voltage, power, and temperature readback via an integrated
12-bit analog-to-digital converter (ADC), accessed using a PMBus™
interface. The load current is measured using an internal current
sense amplifier that measures the voltage across a sense resistor
in the power path via the HS+ and HS− pins. A default current
limit of 20 mV is set, but this limit can be adjusted, if required.
The ADM1278 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage, and therefore
the load current, is maintained below the preset maximum. The
ADM1278 protects the external FET by limiting the time that
the FET remains on while the current is at its maximum value.
This current-limit time is set by the choice of capacitor connected
to the TIMER pin. In addition, a constant power foldback scheme
is used to control the power dissipation in the MOSFET during
power-up and fault conditions. The level of this power, along
with the TIMER regulation time, can be set to ensure that the
MOSFET remains within safe operating area (SOA) limits.
TYPICAL APPLICATION CIRCUIT
4.5V TO 20V
RSENSE
Q1
HS+ MO+
MO– HS–
VCC
VCAP
UV
OV
ISET
PSET
ISTART
LDO
+×50–
ISENSE
ADM1278-1
CHARGE
PUMP
VCP
+
1.0V
GATE
DRIVE/
LOGIC
1.0V +
TIMEOUT
+
REF
+
SELECT
1.0V
CURRENT-
1.0V
HS–
LIMIT
CONTROL
GATE
TEMP
PWGIN
VOUT
VCBOS
TIMER
RETRY
IOUT
TIMER TIMEOUT
HS+
ISENSE
VOUT
TEMP
12-BIT
ADC
LOGIC
AND
PMBus
ANALOG
VOUT
PWRGD
FAULT
ENABLE
GPO2/ALERT2
GPO1/ALERT1/CONV
SCL
SDA
ADR1
ADR2
CSOUT
PGND GND
Figure 1.
In case of a short-circuit event, a fast internal overcurrent
detector responds within 320 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1278 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UV and OV pins. A PWRGD signal can be used to detect when
the output supply is valid, using the PWGIN pin to accurately
monitor the output.
The ADM1278 is available in a 32-lead LFCSP with a RETRY pin
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.
Table 1. Model Options
Model
ADC Accuracy
ADM1278-1AA ±0.3%
ADM1278-1A ±0.7%
ADM1278-1B ±1.0%
ADM1278-2A ±0.7%
ADM1278-3A ±0.7%
SPI Interface
No
No
No
Yes
No
Enable Pin1
Active high
Active high
Active high
Active high
Active low
1 Active high relates to the ENABLE pin, and active low relates to the ENABLE pin.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADM1278 pdf, 반도체, 판매, 대치품
Data Sheet
Manufacturer Specific Status Register......................................51
Read EIN Register.........................................................................52
Read VIN Register ........................................................................52
Read VOUT Register......................................................................53
Read IOUT Register .......................................................................53
Read Temperature 1 Register.....................................................53
Read PIN Register.........................................................................53
PMBus Revision Register...........................................................53
Manufacturer ID Register ..........................................................54
Manufacturer Model Register....................................................54
Manufacturer Revision Register................................................54
Manufacturer Date Register.......................................................54
Peak IOUT Register........................................................................54
Peak VIN Register.........................................................................55
Peak VOUT Register ......................................................................55
Power Monitor Control Register...............................................55
REVISION HISTORY
12/14—Rev. 0 to Rev. A
Changes to Features Section, General Description Section,
and Applications Section..................................................................1
Added Table 1, Renumbered Sequentially .....................................1
Changes to POWER_CYCLE Command Section ......................37
Change to Power Cycle Register Section......................................58
6/14—Revision 0: Initial Version
ADM1278
Power Monitor Configuration Register ...................................55
Alert 1 Configuration Register..................................................56
Alert 2 Configuration Register..................................................57
Peak Temperature Register ........................................................57
Device Configuration Register..................................................57
Power Cycle Register ..................................................................58
Peak PIN Register .........................................................................59
Read PIN (Extended) Register ....................................................59
Read EIN (Extended) Register ....................................................59
Hysteresis Low Level Register ...................................................59
Hysteresis High Level Register..................................................59
Hysteresis Status Register...........................................................60
Start-Up IOUT Limit Register ......................................................60
Outline Dimensions........................................................................61
Ordering Guide ...........................................................................61
Rev. A | Page 3 of 61

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ADM1278 전자부품, 판매, 대치품
ADM1278
Data Sheet
Parameter1
TIMER Pull-Down Current
Retry
Hold
TIMER High Threshold
TIMER Low Threshold
TIMER Glitch Filter
Minimum POR Duration
PSET PIN
Reference Select Threshold
Gain of Current Sense Amplifier
Input Current
VOUT PIN
Input Current
FAULT PIN
Output Low Voltage
Symbol
ITIMERDNRT
ITIMERDNHOLD
VTIMERH
VTIMERL
TIMERGF
VPSETRSTH
AVCSAMP
IPSET
VOL_LATCH
Leakage Current
ENABLE PIN
Input High Voltage
Input Low Voltage
Glitch Filter
RETRY PIN
Input High Voltage
Input Low Voltage
Glitch Filter
Internal Pull-Up Current
CSOUT PIN
CSOUT Gain
Total Output Error
Output Swing to GND
Current Limiting
GPO1/ALERT1/CONV PIN
Output Low Voltage
Leakage Current
Input High Voltage
Input Low Voltage
Glitch Filter
GPO2/ALERT2 PIN
Output Low Voltage
Leakage Current
PWRGD PIN
Output Low Voltage
VCC That Guarantees Valid
Output
Leakage Current
VIH
VIL
VIH
VIL
VOL_GPO1
VIH
VIL
VOL_GPO2
VOL_PWRGD
Min Typ Max Unit Test Conditions/Comments
1.7 2 2.3 µA After fault when GATE is off; VTIMER = 0.5 V
100 µA Holds TIMER at 0 V when inactive; VTIMER = 0.5 V
0.98 1.0 1.02 V
0.18 0.2 0.22 V
10 µs
27 ms Minimum initial insertion delay regardless of CTIMER value
FET power limit = (VPSET × 8)/(50 × RSENSE)
1.35 1.5 1.65 V
If VPSET > VPSETRSTH, constant power is disabled
50 V/V Accuracies included in total sense voltage accuracies
100 nA VPSET ≤ VVCAP
40 μA VOUT = 20 V
0.4 V
IFAULT = 1 mA
1.5 V
IFAULT = 5 mA
100 nA VFAULT ≤ 2 V; FAULT output high-Z
1 µA VFAULT = 20 V; FAULT output high-Z
1.1 V
0.8 V
1 µs
1.1 V Latch off when high; internal pull-up sets this as default
0.8 V
10 second automatic retry when pin pulled low
1 µs
8 µA
−1.6
−3.0
350 V/V CSOUT = VSENSE_HS × 350; VCC > CSOUT + 2 V
+1.6 %
VSENSE_HS = 20 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
+3.0 %
VSENSE_HS = 10 mV; ICSOUT ≤ 1 mA; CCSOUT = 1 nF
40 mV
5 mA CSOUT short-circuit current
0.4 V
IGPO1 = 1 mA
1.5 V
IGPO1 = 5 mA
100 nA VGPO1 ≤ 2 V; GPO1 output high-Z
1 µA VGPO1 = 20 V; GPO1 output high-Z
1.1 V Configured as CONV
0.8 V
Configured as CONV
1 µs Configured as CONV
0.4 V
IGPO2 = 1 mA
1.5 V
IGPO2 = 5 mA
100 nA VGPO2 ≤ 2 V; GPO2 output high-Z
1 µA VGPO2 = 20 V; GPO2 output high-Z
0.4 V
IPWRGD = 1 mA
1.5 V
IPWRGD = 5 mA
1 V ISINK = 100 μA; VOL_PWRGD = 0.4 V
100 nA
1 µA
Rev. A | Page 6 of 61
VPWRGD ≤ 2 V; PWRGD output high-Z
VPWRGD = 20 V; PWRGD output high-Z

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