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Analog Devices에서 제조한 전자 부품 AD5781은 전자 산업 및 응용 분야에서
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부품번호 AD5781 기능
기능 Voltage Output DAC
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AD5781 데이터시트, 핀배열, 회로
Data Sheet
True 18-Bit, Voltage Output DAC
±0.5 LSB INL, ±0.5 LSB DNL
AD5781
FEATURES
Single 18-bit DAC, ±0.5 LSB INL
7.5 nV/√Hz noise spectral density
0.05 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
1.4 nV-sec glitch impulse
Operating temperature range: −40°C to +125°C
20-lead TSSOP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
GENERAL DESCRIPTION
The AD57811 is a single 18-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. The AD5781
accepts a positive reference input range of 5 V to VDD − 2.5 V and
a negative reference input range of VSS + 2.5 V to 0 V. The
AD5781 offers a relative accuracy specification of ±0.5 LSB
maximum, and operation is guaranteed monotonic with a ±0.5
LSB DNL maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V and in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
FUNCTIONAL BLOCK DIAGRAM
VCC
VDD
VREFPF VREFPS
IOVCC
SDIN
SCLK
SYNC
SDO
LDAC
CLR
RESET
AD5781
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
18
DAC 18
REG
18-BIT
DAC
6.8kΩ 6.8kΩ
A1 R1 RFB RFB
INV
VOUT
6kΩ
POWER-ON-RESET
AND CLEAR LOGIC
DGND VSS AGND VREFNF VREFNS
Figure 1.
Table 1. Complementary Devices
Part No.
Description
AD8675
Ultraprecision, 36 V, 2.8 nV/√Hz rail-to-rail
output op amp
AD8676
Ultraprecision, 36 V, 2.8 nV/√Hz dual rail-to-
rail output op amp
ADA4898-1
High voltage, low noise, low distortion, unity
gain stable, high speed op amp
Table 2. Related Devices
Part No.
Description
AD5791
20-bit, 1 ppm accurate DAC
AD5541A/AD5542A 16-bit, 1 LSB accurate 5 V DAC
PRODUCT HIGHLIGHTS
1. True 18-Bit Accuracy.
2. Wide Power Supply Range of Up to ±16.5 V.
3. −40°C to +125°C Operating Temperature Range.
4. Low 7.5 nV/√Hz Noise.
5. Low 0.05 ppm/°C Temperature Drift.
1 Protected by U.S. Patent No 7884747, and other patents are pending.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5781 pdf, 반도체, 판매, 대치품
Data Sheet
AD5781
SPECIFICATIONS
VDD = +12.5 V to +16.5 V, VSS = −16.5 V to −12.5 V, VREFP = +10 V, VREFN = −10 V, VCC = +2.7 V to +5.5 V, IOVCC = +1.71 V to +5.5 V,
RL = unloaded, CL = unloaded, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE2
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
Differential Nonlinearity Error
Linearity Error Long-Term Stability5
Min
18
−0.5
−0.5
−1
−4
−0.5
−0.5
−1
Full-Scale Error
−1.75
−2.75
−5.25
−1
Full-Scale Error Temperature Coefficient3
Zero-Scale Error
−1
−1.5
−1.75
−2.5
−5.25
−1
Zero-Scale Error Temperature Coefficient3
Gain Error
Gain Error Temperature Coefficient3
R1, RFB Matching
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Slew Rate
Output Voltage Settling Time
−1
−1.5
−6
−10
−20
VREFN
Output Noise Spectral Density
Output Voltage Noise
A, B Version1
Typ Max
±0.25 +0.5
±0.25
±0.5
±2
±0.25
±0.25
±0.5
0.04
0.05
0.03
±0.25
±0.062
±0.2
±0.25
+0.5
+1
+4
+0.5
+0.5
+1
+1.75
+2.75
+5.25
+1
±0.062
±0.2
±0.02
±0.025
±0.38
±0.19
±0.025
+1
+1.5
+1.75
+2.5
+5.25
+1
±0.38
±0.19
±0.04
±0.3
±0.4
±0.4
±0.04
0.01
+1
+1.5
+6
+10
+20
VREFP
50
1
1
7.5
7.5
7.5
1.1
Unit Test Conditions/Comments
Bits
LSB B version, VREFP = +10 V, VREFN = −10 V
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR/°C
%
B version, VREFP = +10 V, VREFN = 0 V3
B version, VREFP = +5 V, VREFN = 0 V3
A version4
VREFP = +10 V, VREFN = −10 V
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
After 500 hours at TA = 125°C
After 1000 hours at TA = 125°C
After 1000 hours t TA = 100°C
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
VREFP = +10 V, VREFN = −10 V3,
TA = 0°C to 105°C
VREFP = 10 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = 5 V, VREFN = 0 V3, TA = 0°C to 105°C
VREFP = +10 V, VREFN = −10 V3
VREFP = +10 V, VREFN = 0 V3
VREFP = +5 V, VREFN = 0 V3
V
V/µs
µs
µs
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
Unbuffered output, 10 MΩ||20 pF load
10 V step to 0.02%, using AD845
buffer in unity-gain mode
125 code step to ±1 LSB6
at 1 kHz, DAC code = midscale
at 10 kHz, DAC code = midscale
at 100 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to
10 Hz bandwidth7
Rev. D | Page 3 of 28

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AD5781 전자부품, 판매, 대치품
AD5781
SCLK
SYNC
SDIN
LDAC
VOUT
1
t6
t4
2
t8
DB23
t10
t3
t9
t1
t2
t7
24
t5
DB0
t11
t12
t13
Data Sheet
VOUT
t14
CLR
VOUT
t15
t16
RESET
t21
t22
VOUT
SCLK
SYNC
SDIN
SDO
t17
t6
1
t4
2
Figure 2. Write Mode Timing Diagram
t1 t7
24
t3 t2
t5
12
t17
t20
24
t5
t8
DB23
t9
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB0
NOP CONDITION
t19
DB23
DB0
REGISTER CONTENTS CLOCKED OUT
Figure 3. Readback Mode Timing Diagram
t18
Rev. D | Page 6 of 28

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