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PDF AD5675 Data sheet ( Hoja de datos )
| Número de pieza | AD5675 | |
| Descripción | 16-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5675 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas | ||
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Data Sheet
FEATURES
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/bit)
1.8 V logic compatibility
I2C-compatible serial interface
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
Octal, 16-Bit nanoDAC+
with I2C Interface
AD5675
GENERAL DESCRIPTION
The AD5675 is a low power, octal, 16-bit buffered voltageoutput
digital-to-analog converter (DAC). The device includes a gain
select pin, giving a full-scale output of VREF (gain = 1) or 2 ×
VREF (gain = 2). The device operates from a single 2.7 V to 5.5 V
supply and is guaranteed monotonic by design. The AD5675 is
available in 20-lead TSSOP and LFCSP packages. The power-on
reset circuit and a RSTSEL pin ensure that the output DACs power
up to zero scale or midscale and remain there untila valid write
takes place. The AD5675 contains a power-down mode, reducing
the current consumption to 1 µA typical while in power-down
mode. The AD5675 uses a versatile 2-wire serial interface that
operates at clock rates up to 400 kHz, and includes a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
SPI
Internal
AD5676R
External
AD5676
I2C
Internal
AD5675R
12-Bit
AD5672R
Not applicable
AD5671R
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
VREF
AD5675
SCL
SDA
A1
A0
LDAC
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
2.5V
REF
STRING
DAC 0
BUFFER
STRING
DAC 1
BUFFER
STRING
DAC 2
BUFFER
STRING
DAC 3
BUFFER
STRING
DAC 4
BUFFER
STRING
DAC 5
BUFFER
STRING
DAC 6
BUFFER
STRING
DAC 7
BUFFER
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
POWER-ON
RESET
GAIN POWER-DOWN
×1/×2
LOGIC
RSTSEL
Figure 1.
GAIN
GND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility isassumed by Analog Devicesforitsuse, nor for any infringementsof patentsorother
rightsof third partiesthatmayresult fromitsuse. Specificationssubjecttochangewithout notice.No
licenseisgranted by implication or otherwiseunder any patent or patent rightsof Analog Devices.
Trademarks and registered trademarks are the property oftheir respective owners.
One Technology Way , P.O. Box 910 6, Norwood, MA 0206 2-9106 , U.S .A.
Tel: 78 1.32 9.47 00 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technica l Support
www.analog.com
1 page  
AD5675
Data Sheet
Parameter
LOGIC INPUTS3
Input Current
Input Voltage
Low, VINL
High, VINH
Pin Capacitance
LOGIC OUTPUTS (SDA)3
Output Voltage
Low, VOL
High, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
IDD
Normal Mode 7
All Power-Down Modes8
A Grade
Min Typ Max
±1
0.7 ×
VLOGIC
3
0.3 ×
VLOGIC
VLOGIC −
0.4
4
0.4
1.8
2.7
VREF +
1.5
1.1
1.1
1
1
1
1
5.5
3
3
3
3
5.5
5.5
1.26
1.3
1.7
1.7
2.5
2.5
1 5.5
1 5.5
B Grade
Min Typ Max
±1
0.7 ×
VLOGIC
3
0.3 ×
VLOGIC
VLOGIC −
0.4
4
0.4
1.8
2.7
VREF +
1.5
1.1
1.1
1
1
1
1
1
1
5.5
3
3
3
3
5.5
5.5
1.26
1.3
1.7
1.7
2.5
2.5
5.5
5.5
Unit
µA
V
V
pF
V
V
pF
V
µA
µA
µA
µA
V
V
mA
mA
µA
µA
µA
µA
µA
µA
Test Conditions/Comments
Per pin
ISINK = 200 μA
ISOURCE = 200 μA
Power-on, −40°C to +105°C
Power-on, −40°C to +125°C
Power-down, −40°C to +105°C
Power-down, −40°C to +125°C
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
−40°C to +85°C
−40°C to +125°C
Tristate to 1 kΩ, −40°C to +85°C
Power down to 1 kΩ, −40°C to +85°C
Tristate to 1 kΩ, −40°C to +105°C
Power down to 1 kΩ, −40°C to
+105°C
Tristate to 1 kΩ, −40°C to +125°C
Power down to 1 kΩ, −40°C to
+125°C
1 DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 See the Terminology section.
3 Guaranteed by design and characterization; not production tested.
4 Together, Channel 0, Channel 1, Channel 2, and Channel 3 can source or sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source or
sink 40 mA up to a junction temperature of 125°C.
5 VDD = 5 V. The AD5675 includes current limiting to protect the device during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV.
7 Interface inactive. All DACs active. DAC outputs unloaded.
8 All DACs powered down.
Rev. B | Page 4 of 26
5 Page 
AD5675
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10000
20000 30000 40000 50000
CODE
Figure 6. INL Error vs. Code
60000
70000
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
10000
20000 30000 40000 50000
CODE
Figure 7. DNL Error vs. Code
60000
70000
0.04
0.03
0.02
0.01
0
–0.01
–0.02
0
10000
20000 30000 40000 50000
CODE
Figure 8. TUE vs. Code
60000
70000
Data Sheet
10
8
6
4
2
0
–2
–4
–6
–8 VDD = 5V
TA = 25°C
–10
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 9. INL Error vs. Temperature
100
120
10
8
6
4
2
0
–2
–4
–6 VDD = 5V
TA = 25°C
–8
–10
–40
–20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 10. DNL Error vs. Temperature
120
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
VDD = 5V
TA = 25°C
0.02
0.01
0
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 11. TUE vs. Temperature
100 120
Rev. B | Page 10 of 26
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet AD5675.PDF ] | |
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