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AD5676 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD5676은 전자 산업 및 응용 분야에서
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부품번호 AD5676 기능
기능 16-Bit nanoDAC+
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AD5676 데이터시트, 핀배열, 회로
Data Sheet
Octal, 16-Bit nanoDAC+ with SPI Interface
AD5676
FEATURES
GENERAL DESCRIPTION
High performance
High relative accuracy (INL): ±3 LSB maximum at 16 bits
Total unadjusted error (TUE): ±0.14% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.06% of FSR maximum
Wide operating ranges
−40°C to +125°C temperature range
2.7 V to 5.5 V power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/gain bit)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Robust 2 kV HBM and 1.5 kV FICDM ESD rating
20-lead, TSSOP and LFCSP RoHS-compliant packages
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
Data acquisition systems
The AD5676 is a low power, octal, 16-bit buffered voltage
output digital-to-analog converter (DAC). The device includes
a gain select pin, giving a full-scale output of VREF (gain = 1) or
2 × VREF (gain = 2). The AD5676 DAC operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5676 is available in 20-lead TSSOP and LFCSP packages.
The internal power-on reset circuit and the RSTSEL pin of the
AD5676 ensure that the output DACs power up to zero scale or
midscale and then remain there until a valid write takes place. The
AD5676 contains a per channel power-down mode that typically
reduces the current consumption of the device to 1 µA.
The AD5676 employs a versatile serial peripheral interface (SPI)
that operates at clock rates up to 50 MHz, and contains a VLOGIC pin
intended for 1.8 V to 5.5 V logic.
Table 1. Octal nanoDAC+® Devices
Interface Reference 16-Bit
SPI
Internal
AD5676R
External
AD5676
I2C
Internal
AD5675R
External
AD5675
12-Bit
AD5672R
Not applicable
AD5671R
Not applicable
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL) 16-bit: ±3 LSB maximum.
2. −40°C to +125°C temperature range.
3. 20-lead, TSSOP and LFCSP RoHS-compliant packages.
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
VREF
AD5676
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 0
BUFFER
VOUT0
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 1
BUFFER
VOUT1
SCLK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
BUFFER
VOUT2
SYNC
SDI
INTERFACE
LOGIC
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC 3
STRING
DAC 4
BUFFER
BUFFER
VOUT3
VOUT4
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
BUFFER
VOUT5
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 6
BUFFER
VOUT6
RESET
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
BUFFER
VOUT7
POWER-ON RESET
GAIN x1/x2
POWER-DOWN
LOGIC
RSTSEL
Figure 1.
GAIN
GND
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5676 pdf, 반도체, 판매, 대치품
Data Sheet
AD5676
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Resolution
Relative Accuracy (INL)2
Min
16
Differential Nonlinearity
(DNL)2
Zero Code Error2
Offset Error2
Full-Scale Error2
Gain Error2
Total Unadjusted Error (TUE)
Offset Error Drift2, 3
DC Power Supply Rejection
Ratio (PSRR)2, 3
DC Crosstalk2, 3
OUTPUT CHARACTERISTICS3
Output Voltage Range
Output Current Drive
Capacitive Load Stability
Resistive Load4
Load Regulation
0
0
1
Short-Circuit Current5
Load Impedance at Rails6
Power-Up Time
REFERENCE INPUT
Reference Input Current
Reference Input Range
Reference Input Impedance
1
1
A Grade
Typ Max
±1.8 ±8
±1.7 ±8
±0.7 ±1
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
+0.03
+0.006
±1
0.25
±1
4
±6
±4
±0.28
±0.14
±0.24
±0.12
±0.3
±0.25
±2
±3
±2
Min
16
VREF 0
2 × VREF 0
15
2
10
1
183
177
40
25
2.5
398
789
VDD 1
VDD/2
1
14
7
B Grade
Typ Max
Unit
Test Conditions/Comments
±1.8 ±3
±1.7 ±3
±0.7 ±1
±0.5
0.8
−0.75
−0.1
−0.018
−0.013
+0.04
−0.02
+0.03
+0.006
±1
0.25
±1
1.6
±2
±1.5
±0.14
±0.07
±0.12
±0.06
±0.18
±0.14
±2
±3
±2
Bits
LSB Gain = 1
LSB Gain = 2
LSB Gain = 1
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µV/°C
mV/V
µV
µV/mA
µV
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
DAC code = midscale, VDD = 5 V ±
10%
Due to single channel, full-
scale output change
Due to load current change
Due to powering down (per
channel)
VREF V
Gain = 1
2 × VREF V
Gain = 2
15 mA
2 nF RL = ∞
10 nF RL = 1 kΩ
kΩ
183 µV/mA 5 V ± 10%, DAC code = midscale,
−30 mA ≤ IOUT ≤ +30 mA
177 µV/mA 3 V ± 10%, DAC code = midscale,
−20 mA ≤ IOUT ≤ +20 mA
40 mA
25 Ω
2.5 µs Exiting power-down mode,
VDD = 5 V
398 µA
789 µA
VDD V
VDD/2
V
14 kΩ
7 kΩ
VREF = VDD = VLOGIC = 5.5 V, gain = 1
VREF = VDD = VLOGIC = 5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Rev. B | Page 3 of 27

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AD5676 전자부품, 판매, 대치품
AD5676
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time (Single, Combined, or All Channel Update)
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1.8 V ≤ VLOGIC < 2.7 V
Min Max
20
4
4.5
15.1
0.8
+0.1
0.95
9.65
4.75
4.85
41.25
26.35
4.8
132
5.15
2.7 V ≤ VLOGIC ≤ 5.5 V
Min Max
20
1.7
4.3
10.1
0.8
−0.8
1.25
6.75
9.7
5.45
25
20.3
6.2
80
5.18
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
2 Time to exit power-down to normal mode of AD5676 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
SCLK
SYNC
SDI
LDAC1
t9
t8 t4
DB23
t6
t5
LDAC2
RESET
t13
VOUTx
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t1
t3 t2
t7
DB0
t12
t10
t11
Figure 2. Serial Write Operation
Rev. B | Page 6 of 27

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