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PDF AD5693R Data sheet ( Hoja de datos )
| Número de pieza | AD5693R | |
| Descripción | Tiny 16-/14-/12-Bit I2C nanoDAC+ | |
| Fabricantes | Analog Devices | |
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Data Sheet
Tiny 16-/14-/12-Bit I2C nanoDAC+, with
±2 LSB INL (16-Bit) and 2 ppm/°C Reference
AD5693R/AD5692R/AD5691R/AD5693
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5693R/AD5692R/AD5691R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5693
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): ±0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05 % of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
1.8 V VLOGIC compatible
Wide operating temperature range: −40°C to +105°C
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
Optical modules
GENERAL DESCRIPTION
The AD5693R/AD5692R/AD5691R/AD5693, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage output DACs. The devices, except the AD5693,
include an enabled by default internal 2.5 V reference, offering
2 ppm/°C drift. The output span can be programmed to be 0 V to
VREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to
5.5 V supply and are guaranteed monotonic by design. The
devices are available in a 2.00 mm × 2.00 mm, 8-lead LFCSP or
a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5693R/AD5692R/
AD5691R/AD5693 contain a power-down mode that reduces the
current consumption of the device to 2 µA (maximum) at 5 V and
provides software selectable output loads.
The AD5693R/AD5692R/AD5691R/AD5693 use an I2C
interface. Some device options also include an asynchronous
RESET pin and a VLOGIC pin, allowing 1.8 V compatibility.
LDAC
RESET
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
16-/14-/12-BIT
DAC
AD5693R/
AD5692R/
AD5691R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SDA SCL
A0 GND
Figure 1. MSOP
LDAC OR VLOGIC OR RESET1 VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V REF2
AD5693R/
AD5692R/
AD5691R/
AD5693
REF
16-/14-/12-BIT
DAC
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SDA SCL
A0
GND
1NOT ALL PINS AVAILABLE IN ALL 8-LEAD LFCSP MODELS.
2NOT AVAILABLE IN THE AD5693.
Figure 2. LFCSP
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
16-Bit
AD5683R
AD5683
AD5693R
AD5693
14-Bit
AD5682R
AD5692R
12-Bit
AD5681R
AD5691R
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL): ±2 LSB maximum
(AD5693R/AD5693, 16-bit).
2. Low drift, 2.5 V on-chip reference: 2 ppm/°C typical and
5 ppm/°C maximum temperature coefficient.
3. 2 mm × 2 mm, 8-lead LFCSP and 10-lead MSOP.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5693R/AD5692R/AD5691R/AD5693
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V to VDD − 0.2 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C,
typical at 25°C, unless otherwise noted.
Table 3.
Parameter
Output Voltage Settling Time1, 2
Slew Rate
Digital-to-Analog Glitch Impulse1
Digital Feedthrough1
Total Harmonic Distortion1
Output Noise Spectral Density1
Output Noise
SNR
SFDR
SINAD
Typ Max Unit
Conditions/Comments
57
µs
Gain = 1
0.7 V/µs
0.1 nV-s ±1 LSB change around major carry, gain = 2
0.1 nV-s
−80 dB At ambient temperature, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
300 nV/√Hz DAC code = midscale, 10 kHz
6 µV p-p 0.1 Hz to 10 Hz; internal reference
90 dB At ambient temperature, bandwidth (BW) = 20 kHz, VDD =5 V, fOUT = 1 kHz
83 dB At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz
80 dB At ambient temperature, BW = 20 kHz, VDD =5 V, fOUT = 1 kHz
1 See the Terminology section.
2 For the AD5693R/AD5693, to ±2 LSB. For the AD5692R, to ±1 LSB. For the AD5691R, to ±0.5 LSB
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC = 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter1
fSCL2
t1
t2
t3
t4 3
t5
t6
t7
t8
t9
t104
t11
t124
tSP5
t13
t14
t15
t16
tREF_POWER_UP 6
tSHUTDOWN 7
Min Typ
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20 × (VDD/5.5 V)
20
20 × (VDD/5.5 V)
0
400
400
20
75
600
Max
400
0.9
300
300
300
300
50
6
Unit Description
kHz Serial clock frequency
µs SCL high time, tHIGH
µs SCL low time, tLOW
ns Data setup time, tSU; DAT
µs Data hold time, tHD; DAT
µs Setup time for a repeated start condition, tSU; STA
µs Hold time (repeated) start condition, tHD; STA
µs Bus free time between a stop and a start condition, tBUF
µs Setup time for a stop condition, tSU; STO
ns Rise time of SDA signal, tr
ns Fall time of SDA signal, tf
ns Rise time of SCL signal, tr
ns Fall time of SCL signal, tf
ns Pulse width of suppressed spike (not shown in Figure 3)
ns LDAC falling edge to SCL falling edge
ns LDAC pulse width (synchronous mode)
ns LDAC pulse width (asynchronous mode)
ns RESET pulse width
µs Reference power-up (not shown in Figure 3)
µs Exit shutdown (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the device.
3 The master should add at least 300 ns for the SDA signal (with respect to the VOH (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL.
4 Substitute VLOGIC for VDD on devices that include a VLOGIC pin.
5 Not applicable for standard mode.
6 Expect the same timing when powering up the device after VDD is equal to 2.7 V.
7 Time to exit power-down to normal mode of AD5693R/AD5692R/AD5691R/AD5693 operation.
Rev. D | Page 5 of 26
5 Page 
Data Sheet
AD5693R/AD5692R/AD5691R/AD5693
VDD 1
RESET 2
GND 3
A0 4
AD5693R-2
TOP VIEW
(Not to Scale)
8 VOUT
7 VREF
6 SDA
5 SCL
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
Figure 8. AD5693R-2 Pin Configuration, 8-Lead LFCSP, RESET Option
Table 10. AD5693R-2 Pin Function Descriptions, 8-Lead LFCSP, RESET Option
Pin No. Mnemonic Description
1 VDD
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2
RESET
Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins
are ignored. The input and DAC registers are loaded with zero code value and the control register is loaded with
default values. Tie this pin to VDD if not used. If this pin is forced low at power-up, the power-on reset (POR) circuit
does not initialize the device correctly until this pin is released.
3 GND Ground Reference.
4 A0
Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.
5 SCL
Serial Clock Line.
6 SDA Serial Data Input/Output.
7 VREF
Reference Input/Output. In the AD5693R-2, this is a reference output pin by default. It is recommended to use a
10 nF decoupling capacitor for the internal reference.
8 VOUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EPAD
Exposed Pad. Connect the exposed pad to GND.
Rev. D | Page 11 of 26
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AD5693R.PDF ] | |
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