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부품번호 AD5693 기능
기능 Tiny 16-/14-/12-Bit I2C nanoDAC+
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AD5693 데이터시트, 핀배열, 회로
Data Sheet
Tiny 16-/14-/12-Bit I2C nanoDAC+, with
±2 LSB INL (16-Bit) and 2 ppm/°C Reference
AD5693R/AD5692R/AD5691R/AD5693
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5693R/AD5692R/AD5691R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5693
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): ±0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05 % of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
1.8 V VLOGIC compatible
Wide operating temperature range: −40°C to +105°C
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
Optical modules
GENERAL DESCRIPTION
The AD5693R/AD5692R/AD5691R/AD5693, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage output DACs. The devices, except the AD5693,
include an enabled by default internal 2.5 V reference, offering
2 ppm/°C drift. The output span can be programmed to be 0 V to
VREF or 0 V to 2 × VREF. All devices operate from a single 2.7 V to
5.5 V supply and are guaranteed monotonic by design. The
devices are available in a 2.00 mm × 2.00 mm, 8-lead LFCSP or
a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5693R/AD5692R/
AD5691R/AD5693 contain a power-down mode that reduces the
current consumption of the device to 2 µA (maximum) at 5 V and
provides software selectable output loads.
The AD5693R/AD5692R/AD5691R/AD5693 use an I2C
interface. Some device options also include an asynchronous
RESET pin and a VLOGIC pin, allowing 1.8 V compatibility.
LDAC
RESET
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V
REF
REF
16-/14-/12-BIT
DAC
AD5693R/
AD5692R/
AD5691R
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SDA SCL
A0 GND
Figure 1. MSOP
LDAC OR VLOGIC OR RESET1 VREF
VDD
POWER-ON
RESET
DAC
REGISTER
2.5V REF2
AD5693R/
AD5692R/
AD5691R/
AD5693
REF
16-/14-/12-BIT
DAC
OUTPUT
BUFFER
VOUT
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SDA SCL
A0
GND
1NOT ALL PINS AVAILABLE IN ALL 8-LEAD LFCSP MODELS.
2NOT AVAILABLE IN THE AD5693.
Figure 2. LFCSP
Table 1. Related Devices
Interface
Reference
SPI Internal
External
I2C Internal
External
16-Bit
AD5683R
AD5683
AD5693R
AD5693
14-Bit
AD5682R
AD5692R
12-Bit
AD5681R
AD5691R
PRODUCT HIGHLIGHTS
1. High relative accuracy (INL): ±2 LSB maximum
(AD5693R/AD5693, 16-bit).
2. Low drift, 2.5 V on-chip reference: 2 ppm/°C typical and
5 ppm/°C maximum temperature coefficient.
3. 2 mm × 2 mm, 8-lead LFCSP and 10-lead MSOP.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD5693 pdf, 반도체, 판매, 대치품
AD5693R/AD5692R/AD5691R/AD5693
Data Sheet
Parameter
REFERENCE OUTPUT
Output Voltage
Voltage Reference TC3
A Grade
B Grade
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Capacitive Load Stability
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
Thermal Hysteresis
REFERENCE INPUT
Reference Current
Reference Input Range4
Reference Input Impedance
LOGIC INPUTS
IIN, Input Current
VINL, Input Low Voltage4
VINH, Input High Voltage4
CIN, Pin Capacitance
LOGIC OUTPUTS (SDA)4
Output Low Voltage, VOL
Output High Voltage, VOH
Pin Capacitance
POWER REQUIREMENTS
VLOGIC 5
ILOGIC5
VDD
IDD 6
Normal Mode7
Power-Down Modes8
Min
2.4975
Typ
5
2
0.05
16.5
240
5
50
30
±5
80
125
25
35
57
120
60
0.7 × VDD
2
VDD − 0.4
4
1.62
2.7
VREF + 1.5
0.25
350
110
Max Unit Test Conditions/Comments
2.5025
20
5
V
ppm/°C
ppm/°C
µV p-p
nV/√Hz
µF
µV/mA
µV/mA
mA
µV/V
ppm
ppm
At ambient temperature
See the Terminology section
0.1 Hz to 10 Hz
At ambient temperature, f = 10 kHz, CL = 10 nF
RL = 2 kΩ
At ambient temperature, VDD ≥ 3 V
At ambient temperature
VDD ≥ 3 V
At ambient temperature
First cycle
Additional cycles
µA
µA
VDD V
kΩ
kΩ
VREF = VDD = VLOGIC = 5.5 V, gain = 1
VREF = VDD = VLOGIC = 5.5 V, gain = 2
Gain = 1
Gain = 2
±1
±3
0.3 × VDD
µA
µA
V
V
pF
Per pin
SDA and SCL pins
0.4 V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
5.5 V
3 µA
5.5 V
5.5 V
500 µA
180 µA
2 µA
VIH = VLOGIC or VIL = GND
Gain = 1
Gain = 2
VIH = VDD, VIL = GND
Internal reference enabled
Internal reference disabled
1 Linearity calculated using a reduced code range: AD5693R/AD5693 (Code 512 to Code 65,535); AD5692R (Code 128 to Code 16,384); AD5691R (Code 32 to Code 4096).
Output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage with 20 Ω, 1 mA generates 20 mV. See Figure 36 for more details.
3 Voltage reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4 Substitute VLOGIC for VDD if the device includes a VLOGIC pin.
5 The VLOGIC pin is not available on all models.
6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC.
7 Interface inactive. DAC active. DAC output unloaded.
8 DAC powered down.
Rev. D | Page 4 of 26

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AD5693 전자부품, 판매, 대치품
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND1
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
−40°C to +105°C
−65°C to +150°C
135°C
(TJ max − TA)/θJA
1 Substitute VDD with VLOGIC on devices that include a VLOGIC pin.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD5693R/AD5692R/AD5691R/AD5693
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance1
Package Type
θJA θJC Unit
8-Lead LFCSP
90 25 °C/W
10-Lead MSOP
135 N/A °C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
Rev. D | Page 7 of 26

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