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PDF AD5689R Data sheet ( Hoja de datos )
| Número de pieza | AD5689R | |
| Descripción | Dual 16-/12-Bit nanoDAC+ | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual, 16-/12-Bit nanoDAC+
with 2 ppm/°C Reference, SPI Interface
AD5689R/AD5687R
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD ratings
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5689R/AD5687R members of the nanoDAC+™
family are low power, dual, 16-/12-bit buffered voltage output
digital-to-analog converters (DACs). The devices include
a 2.5 V, 2 ppm/°C internal reference (enabled by default)
and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic
by design, and exhibit less than 0.1% FSR gain error and
1.5 mV offset error performance. Both devices are available
in a 3 mm × 3 mm LFCSP and a TSSOP package.
The AD5689R/AD5687R also incorporate a power-on reset
circuit and a RSTSEL pin that ensure that the DAC outputs
power up to zero scale or midscale and remain there until
a valid write takes place. Each part contains a per channel
power-down feature that reduces the current consumption
of the device to 4 µA at 3 V while in power-down mode.
The AD5689R/AD5687R use a versatile serial peripheral
interface (SPI) that operates at clock rates up to 50 MHz.
and both devices contain a VLOGIC pin that is intended for
1.8 V/3 V/5 V logic.
VLOGIC
SCLK
SYNC
SDIN
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5689R/AD5687R
2.5V
REFERENCE
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
BUFFER
VOUT A
VOUT B
SDO
LDAC RESET
POWER-ON
RESET
GAIN =
×1/×2
RSTSEL
Figure 1.
GAIN
POWER-
DOWN
LOGIC
Table 1. Dual nanoDAC+ Devices
Interface
Reference
16-Bit
SPI
Internal
AD5689R
External
AD5689
I2C
Internal
N/A
External
N/A
12-Bit
AD5687R
AD5687
AD5697R
N/A
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5689R (16-bit): ±2 LSB maximum
AD5687R (12-bit): ±1 LSB maximum
2. Low Drift 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5689R/AD5687R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise
noted. Guaranteed by design and characterization; not production tested.
Table 3.
Parameter1
Output Voltage Settling Time
AD5689R
AD5687R
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion (THD)3
Output Noise Spectral Density (NSD)
Output Noise
Signal-to-Noise Ratio (SNR)
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise-and-Distortion Ratio (SINAD)
Min Typ
Max Unit
Test Conditions/Comments2
58
57
0.8
0.5
0.13
0.1
0.2
0.3
−80
300
6
90
83
80
µs
µs
V/µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 See the Terminology section.
2 Temperature range is −40°C to +105°C, typical at 25°C.
3 Digitally generated sine wave at 1 kHz.
Rev. A | Page 5 of 28
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.5020
2.5015
2.5010
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
VDD = 5V
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 8. Internal Reference Voltage vs. Temperature (Grade B)
2.5020
2.5015
2.5010
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
–40 –20
0
VDD = 5V
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 9. Internal Reference Voltage vs. Temperature (Grade A)
90
VDD = 5V
80
70
60
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE DRIFT (ppm/°C)
Figure 10. Reference Output Temperature Drift Histogram
AD5689R/AD5687R
1600 VDD = 5V
TA = 25°C
1400
1200
1000
800
600
400
200
0
10 100 1k 10k 100k 1M
FREQUENCY (MHz)
Figure 11. Internal Reference Noise Spectral Density vs. Frequency
VDD = 5V
TA = 25°C
T
1
CH1 10µV
M1.0s
A CH1 160mV
Figure 12. Internal Reference Noise, 0.1 Hz to 10 Hz
2.5000
2.4999
VDD = 5V
TA = 25°C
2.4998
2.4997
2.4996
2.4995
2.4994
2.4993
–0.005
–0.003
–0.001
0.001
ILOAD (A)
0.003
0.005
Figure 13. Internal Reference Voltage vs. Load Current
Rev. A | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5689R.PDF ] | |
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