AD5689 Datasheet PDF - Analog Devices
| Part Number | AD5689 | |
| Description | Dual 16-/12-Bit nanoDAC+ | |
| Manufacturers | Analog Devices | |
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Data Sheet
FEATURES
High relative accuracy (INL): ±2 LSB maximum at 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
TUE: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User-selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD ratings
Low power: 3.3 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Optical transceivers
Base station power amplifiers
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
GENERAL DESCRIPTION
The AD5689/AD5687 members of the nanoDAC+™ family are
low power, dual, 16-/12-bit, buffered voltage output digital-to-
analog converters (DACs). The devices include a gain select pin
giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The
AD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, are
guaranteed monotonic by design, and exhibit less than 0.1% FSR
gain error and 1.5 mV offset error performance. Both devices are
available in a 3 mm × 3 mm LFCSP and a TSSOP package.
The AD5689/AD5687 also incorporate a power-on reset circuit
and a RSTSEL pin that ensure that the DAC outputs power up
to zero scale or midscale and remain there until a valid write
takes place. Each part contains a per channel power-down feature
that reduces the current consumption of the device to 4 µA at
3 V while in power-down mode.
The AD5689/AD5687 use a versatile serial peripheral interface
that operates at clock rates up to 50 MHz. Both devices contain
a VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.
Dual, 16-/12-Bit nanoDAC+
with SPI Interface
AD5689/AD5687
VLOGIC
SCLK
SYNC
SDIN
SDO
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
VREF
AD5689/AD5687
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
BUFFER
VOUTA
VOUTB
LDAC RESET
POWER-ON
RESET
GAIN =
×1/×2
RSTSEL
Figure 1.
GAIN
POWER-
DOWN
LOGIC
Table 1. Related Devices
Interface Reference
SPI Internal
External
I2C Internal
External
16-Bit
AD5689R
AD5689
Not applicable
Not applicable
12-Bit
AD5687R
AD5687
AD5697R
Not applicable
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5689 (16-bit): ±2 LSB maximum
AD5687 (12-bit): ±1 LSB maximum
2. Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
3. Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Sheet
AD5689/AD5687
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Power-Up Time
1.8 V ≤ VLOGIC < 2.7 V
Min Max
33
16
16
15
5
5
15
20
16
25
30
20
30
30
4.5
2.7 V ≤ VLOGIC ≤ 5.5 V
Min Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Unit Description
ns SCLK cycle time
ns SCLK high time
ns SCLK low time
ns SYNC to SCLK falling edge setup time
ns Data setup time
ns Data hold time
ns SCLK falling edge to SYNC rising edge
ns Minimum SYNC high time (update single channel or both channels)
ns SYNC falling edge to SCLK fall ignore
ns LDAC pulse width low
ns SCLK falling edge to LDAC rising edge
ns SCLK falling edge to LDAC falling edge
ns RESET minimum pulse width low
ns RESET pulse activation time
µs Time that is required to exit power-down mode and enter
normal mode of operation; 24th clock edge to 90% of DAC
midscale value with output unloaded
1 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 2.7 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
SCLK
SYNC
SDIN
LDAC1
LDAC2
RESET
t9 t1
t8 t4
t3
DB23
t6
t5
t2 t7
DB0
t12
t10
t11
t13
VOUTX
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 5 of 24
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AD5689 electronic component. |
| Information | Total 24 Pages | |
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| Download | [ AD5689.PDF Datasheet ] | |
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