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부품번호 AD7292 기능
기능 10-Bit Monitor and Control System
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AD7292 데이터시트, 핀배열, 회로
Data Sheet
10-Bit Monitor and Control System with ADC,
DACs, Temperature Sensor, and GPIOs
AD7292
FEATURES
10-bit SAR ADC
8 multiplexed analog input channels
Single-ended mode of operation
Differential mode of operation
5 V analog input range
VREF, 2 × VREF, or 4 × VREF input ranges
Input measured with respect to AGND or VDD
4 monotonic, 10-bit, 5 V DACs
2 µs settling time
Power-on reset to 0 V
10 mA sink and source capability
Internal temperature sensor
±1°C accuracy
12 general-purpose digital I/O pins
Internal 1.25 V reference
Built-in monitoring features
Minimum and maximum value register for each channel
Programmable alert thresholds
Programmable hysteresis
SPI interface
Temperature range: −40°C to +125°C
Package type: 36-lead LFCSP
APPLICATIONS
Base station power amplifier (PA) monitoring and control
RF control loops
Optical communication system control
General-purpose system monitoring and control
GENERAL DESCRIPTION
The AD7292 contains all the functionality required for general-
purpose monitoring of analog signals and control of external
devices, integrated into a single-chip solution. The AD7292
features an 8-channel, 10-bit SAR ADC, four 10-bit DACs, a
±1°C accurate internal temperature sensor, and 12 GPIOs to
aid system monitoring and control.
The 10-bit, high speed, low power successive approximation
register (SAR) ADC is designed to monitor a variety of single-
ended input signals. Differential operation is also available by
configuring VIN0 and VIN1 to operate as a differential pair.
The AD7292 offers a register programmable ADC sequencer,
which enables the selection of a programmable sequence of
channels for conversion.
FUNCTIONAL BLOCK DIAGRAM
REFOUT
REFIN DVDD AVDD VDRIVE
TEMPERATURE
SENSOR
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
MUX T/H
BUF
1.25V
REF
÷4
BUF
10-BIT
SAR ADC
CONTROL
LOGIC
ALERT AND LIMIT
REGISTERS
AD7292
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
VOUT0
VOUT1
VOUT2
VOUT3
DIGITAL I/Os
SPI
INTERFACE
Figure 1.
Four 10-bit digital-to-analog converters (DACs) provide outputs
from 0 V to 5 V. An internal, high accuracy, 1.25 V reference
provides a separately buffered reference source for both the ADC
and the DACs.
A high accuracy band gap temperature sensor is monitored and
digitized by the 10-bit ADC to give a resolution of 0.03125°C.
The AD7292 also features built-in limit and alarm functions.
The AD7292 is a highly integrated solution offered in a 36-lead
LFCSP package with an operating temperature range of −40°C
to +125°C.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD7292 pdf, 반도체, 판매, 대치품
Data Sheet
AD7292
SPECIFICATIONS
ADC SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C,
unless otherwise noted. Specifications apply to single-ended mode only, unless otherwise noted.
Table 1.
Parameter
DC ACCURACY
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error
Offset Error Matching
Offset Error Drift
Gain Error
Gain Error Matching
Gain Error Drift
DYNAMIC PERFORMANCE1
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion (SINAD)
Ratio
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel-to-Channel Isolation
Full Power Bandwidth
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
Min
10
Typ
±0.11
±0.1
±3
0.5
±0.22
±0.09
±0.5
±4.17
61.5
61.5
−84
84.5
−80
60
3
900
ANALOG INPUT
Single-Ended Input Range
With Respect to AGND
With Respect to AVDD
Fully Differential Input Range
Input Capacitance
DC Input Leakage Current
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature Coefficient
0
0
0
AVDD − 4 × VREF
−4 × VREF
−2 × VREF
−VREF
23
18
15
1.245
1.25
±13
Max
±0.5
±0.6
±0.99
±8
±12
±1
±0.25
±0.36
45
625
150
Unit
Bits
LSB
LSB
LSB
mV
mV
mV
ppm/°C
% FS
% FS
% FS
ppm/°C
dB
dB
dB
dB
dB
MHz
MHz
ns
ns
kSPS
kSPS
Test Conditions/Comments
(AVDD − 4 × VREF) to AVDD input range
(AVDD − 4 × VREF) to AVDD input range
(AVDD − 4 × VREF) to AVDD input range
fIN = 10 kHz sine wave
fIN = 3 kHz to 1000 kHz
At −3 dB (0 V to VREF input range)
At −0.1 dB (0 V to VREF input range)
See Table 5
ADC only; temperature sensor
disabled
ADC and temperature sensor
4 × VREF
2 × VREF
VREF
AVDD
+4 × VREF
+2 × VREF
+VREF
±1
1.255
V
V
V
V
V
V
V
pF
pF
pF
µA
V
ppm/°C
VIN0 and VIN1 inputs only
0 V to VREF input range
0 V to 2 × VREF input range
0 V to 4 × VREF input range
At 25°C
Rev. A | Page 3 of 40

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AD7292 전자부품, 판매, 대치품
AD7292
Data Sheet
TIMING SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, CL = 27 pF, TA = −40°C
to +125°C, unless otherwise noted.1
Table 5.
Parameter
tCONVERT
tACQ
fSCLK
t1
t2
t3
t4
t5
t63
t7
t8
t9
t10
t114
t12
Description
ADC conversion time/BUSY high time
Temperature sensor disabled
Temperature sensor enabled
ADC acquisition time
Frequency of serial read clock2
SCLK period
SCLK low
SCLK high
CS falling edge to SCLK rising edge
DIN setup time to SCLK falling edge
DIN hold time after SCLK falling edge
SCLK falling edge to CS rising edge
CS high
SCLK to output data valid delay time
SCLK to output data valid hold time
CS rising edge to SCLK rising edge
CS rising edge to DOUT high impedance
VDRIVE = 1.8 V
Limit at TMIN/TMAX
VDRIVE = 2.7 V to 5.25 V
Unit
950 950 ns max
5.85 5.85 μs max
50 50 ns max
15 25 MHz max
66 40 ns min
33 20 ns min
33 20 ns min
4 4 ns min
4 4 ns min
2 2 ns max
5 5 ns min
5 5 ns min
30 19 ns max
7 5 ns min
4 4 ns min
15 15 ns max
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE).
2 For VDRIVE = 2.5 V, fSCLK = 22 MHz maximum.
3 Time required for the output to cross 0.2 × VDRIVE and 0.8 × VDRIVE when VDRIVE = 1.8 V; time required for the output to cross 0.3 × VDRIVE and 0.7 × VDRIVE when VDRIVE = 2.7 V to 5.25 V.
4 Guaranteed by design.
Timing Diagram
BUSY2
CS
SCLK
DIN
t4
t5
XR
t6
W D5
D4
DOUT1
HIGH-Z
1PROVIDED THE READ BIT IS SET.
2IF AN ADC CONVERSION IS REQUESTED.
t7 = 5ns IF NO ADC CONVERSION
955ns WITH ADC CONVERSION
t3
t2
D3 D2 D1 D0
t9
t1
LSB
t10
Figure 2. Serial Interface Timing Diagram
t7
LSB
X
t8
t11
HIGH-Z
t12
Rev. A | Page 6 of 40

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