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ADP5065 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP5065은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ADP5065 기능
기능 Fast Charge Battery Manager
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ADP5065 데이터시트, 핀배열, 회로
Data Sheet
Fast Charge Battery Manager with Power
Path and USB Compatibility
ADP5065
FEATURES
3 MHz switch mode charger
1.25 A charge current from dedicated charger
Up to 680 mA charging current from 500 mA USB host
Operating input voltage from 4.0 V up to 5.5 V
Tolerant input voltage −0.5 V to +20 V (USB VBUS)
Dead battery isolation FET between battery and
charger output
Battery thermistor input with automatic charger shutdown
for when battery temperature exceeds limits
Compliant with the JEITA Li-Ion battery charging
temperature specification
SYS_EN_OK flag to hold off system turn-on until battery is at
minimum required level for guaranteed system startup
due to minimum battery voltage and/or minimum battery
charge level requirements
EOC programming with C/20, C/10 and specific current level
selection
FUNCTIONAL BLOCK DIAGRAM
AC VBUS VINx
OR
USB
CFILT
ADP5065
SWx
SYSTEM
INDUCTOR
3MHz
BUCK
PGNDx
IIN_EXT
TRK_EXT
SCL
SDA
SYS_ON_OK
CHARGER
CONTROL
BLOCK
ISO_Sx
ISO_Bx
BAT_SNS
THR Li-Ion+
V_WEAK_SET AGND PGNDx
Figure 1.
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDA, audio, GPS devices
Mobile phones
GENERAL DESCRIPTION
The ADP5065 charger is fully compliant with the USB 2.0,
USB 3.0, and USB Battery Charging Specification 1.1 and
enables charging via the mini USB VBUS pin from a wall
charger, car charger, or USB host port.
The ADP5065 operates from a 4 V to 5.5 V input voltage range
but is tolerant of voltages of up to 20 V. This alleviates the
concerns about the USB bus spiking during disconnect or
connect scenarios.
The ADP5065 also features an internal FET between the dc-to-
dc charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
scenario, which allows for immediate system function on
connection to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5065 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5065 comes in a very small and low profile 20-lead
WLCSP (0.5 mm pitch spacing) package.
The overall solution requires only five small, low profile external
components consisting of four ceramic capacitors (one of which
is the battery filter capacitor), one multilayer inductor. In addition
to these components, there is one optional dead battery situation
default setting resistor. This configuration enables a very small
PCB area to provide an integrated and performance enhancing
solution to USB battery charging and power rail provision.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5065 pdf, 반도체, 판매, 대치품
Data Sheet
ADP5065
SPECIFICATIONS
−40°C < TJ < 125°C, VIN = 5.0 V, VISO_S > 3.0 V, VHOT < VTHR < VCOLD, VBAT_SNS = 3.6 V, CVIN = 2.2 µF, CDCDC = 22 µF, CBAT = 22 µF, CCFILT =
4.7 µF, LOUT = 1 µH, all registers are at default values, unless otherwise noted.
Table 1.
Parameter
GENERAL PARAMETERS
Undervoltage Lockout
Total Input Current
Current Consumption
VINx
Battery, Standby
SWxPin Leakage Current
CHARGING PARAMETERS
Fast Charge Current, CC Mode
(Battery Voltage > VTRK_DEAD)
Fast Charge Current Accuracy
Symbol
VUVLO
IVIN
Min
2.25
50
86
Typ
2.35
100
92
460 475
IQVIN
IQISO_B
−IOUT
ICHG
ICHG(TOL)
−7
−8
15
0.22
1250
Max
2.45
150
100
150
300
500
900
1500
2
2
+5
+8
−17
Trickle Charge Current1, 2
Weak Charge Current
Dead Battery
Trickle to Weak Charge Threshold
Trickle to Weak Charge Threshold
Hysteresis
Weak Battery
Weak to Fast Charge Threshold
Weak Battery Threshold Hysteresis
Battery Termination Voltage
Battery Termination Voltage Accuracy
Battery Overvoltage Threshold
Charge Complete Current
Charge Complete Current Threshold
Accuracy
Recharge Voltage Differential
Battery Node Short Threshold Voltage1
CHARGER DC-to-DC CONVERTER
Switching Frequency
Maximum Duty Cycle
Peak Inductor Current
Regulated System Voltage
Load Regulation
DC-to-DC Power
PMOS On Resistance
NMOS On Resistance
ITRK_DEAD
ICHG_WEAK
VTRK_DEAD
ΔVTRK_DEAD
VWEAK
ΔVWEAK
VTRM
VBATOV
IEND
VRCH
VBAT_SHR
fSWCHG
DMAX
IL(PK)
VISO_STRK
RDS(ON)P
RDS(ON)N
16
2.4
2.9
4.158
−0.3
−25
−35
−55
2.3
2.8
1500
3.21
20
ICHG + 20
2.5
90
+8
25
2.6
3.0
90
4.200
VCFILT − 0.15
52.5
3.1
4.242
+0.3
+25
+35
+55
260
2.4 2.5
3
96
1750
3.3
5
3.2
2000
3.39
220 285
160 210
Unit Test Conditions/Comments
V Falling threshold, higher of VCFILT and VBAT_SNS
mV Hysteresis, higher of VCFILT and VBAT_SNS rising
mA Nominal USB initialized current level1
mA USB super speed
mA USB enumerated current level (specification
for China)
mA USB enumerated current level
mA Dedicated charger input
mA Dedicated wall charger
mA No battery, no ISO_Sx load, switching 3 MHz
µA TJ = −40°C to +85°C
µA VVIN = 0 V, TJ = −40°C to +85°C
mA
VCFILT > VBAT_SNS + VCCDROP1, 2
% Tj = 25°C, ICHG = 550 mA to 1250 mA
% ICHG = 550 mA to 1150 mA, fast charge current
accuracy is guaranteed at temperatures from
Tj = 0°C to isothermal regulation limit (typically
Tj = 115°C)
% ICHG = 1250 mA, Tj = 0°C to isothermal regulation
limit (typically Tj = 115°C)
mA
mA
When VTRK_DEAD < VBAT_SNS < VWEAK1, 3
V On BAT_SNS1
mV
V On BAT_SNS1, 3
mV
V On BAT_SNS, TJ = 0°C to 115°C1
% On BAT_SNS, TJ = 25°C, IEND = 52.5 mA1
V Relative to CFILT voltage, BAT_SNS rising
mA
VBAT_SNS = VTRM1
% IEND = 72.5 mA or 92.5 mA, TJ = 0°C to 115°C
% IEND = 52.5 mA, TJ = 0°C to 115°C
% IEND = 32.5 mA, TJ = 0°C to 115°C
mV Relative to VTRM, BAT_SNS falling1
V
MHz
%
mA
V
mV/A
VBAT_SNS < VTRK_DEAD, trickle charging mode
Rev. D | Page 3 of 40

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ADP5065 전자부품, 판매, 대치품
ADP5065
Data Sheet
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter1
I2C-COMPATIBLE INTERFACE2
Capacitive Load, Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time Between a Stop and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL/SDA
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
Symbol
CS
fSCL
tHIGH
tLOW
tSUDAT
tHDDAT
tSUSTA
tHDSTA
tBUF
tSUSTO
tR
tF
tSP
Min Typ Max Unit
400 pF
400 kHz
0.6 µs
1.3 µs
100 ns
0 0.9 µs
0.6 µs
0.6 µs
1.3 µs
0.6 µs
20 300 ns
20 300 ns
0 50 ns
1 Guaranteed by design.
2 A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 2, the I2C timing
diagram.
Timing Diagram
SDA
tLOW tR tSU,DAT
tF tF
tHD,STA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
tHD,DAT
tHIGH
tSU,STA
Sr
Figure 2. I2C Timing Diagram
tSP tR
tBUF
tSU,STO
PS
Rev. D | Page 6 of 40

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