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PDF ADP1740 Data sheet ( Hoja de datos )
| Número de pieza | ADP1740 | |
| Descripción | Low Dropout Linear Regulator | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
Maximum output current: 2 A
Input voltage range: 1.6 V to 3.6 V
Low shutdown current: 2 µA
Low dropout voltage: 160 mV at 2 A load
Initial accuracy: ±1%
Accuracy over line, load, and temperature: ±2%
7 fixed output voltage options with soft start:
0.75 V to 2.5 V (ADP1740)
Adjustable output voltage options with soft start:
0.75 V to 3.3 V (ADP1741)
High PSRR
65 dB at 1 kHz
65 dB at 10 kHz
54 dB at 100 kHz
23 μV rms at 0.75 V output
Stable with small 4.7 µF ceramic output capacitor
Excellent load and line transient response
Current-limit and thermal overload protection
Power-good indicator
Logic-controlled enable
Reverse current protection
APPLICATIONS
Server computers
Memory components
Telecommunications equipment
Network equipment
DSP/FPGA/microprocessor supplies
Instrumentation equipment/data acquisition systems
GENERAL DESCRIPTION
The ADP1740/ADP1741 are low dropout (LDO) CMOS linear
regulators that operate from 1.6 V to 3.6 V and provide up to 2 A
of output current. These low VIN/VOUT LDOs are ideal for regu-
lation of nanometer FPGA geometries operating from 2.5 V down
to 1.8 V I/O rails, and for powering core voltages down to 0.75 V.
Using an advanced, proprietary architecture, the ADP1740/
ADP1741 provide high power supply rejection ratio (PSRR) and
low noise, and achieve excellent line and load transient response
with only a small 4.7 µF ceramic output capacitor.
The ADP1740 is available in seven fixed output voltage options.
The ADP1741 is an adjustable version that allows output
2 A, Low VIN, Low Dropout
Linear Regulator
ADP1740/ADP1741
TYPICAL APPLICATION CIRCUITS
VIN = 1.8V
VOUT = 1.5V
4.7µF
100kΩ
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1740 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
SENSE 9
PG GND SS NC
5678
10nF
4.7µF
VIN = 1.8V
Figure 1. ADP1740 with Fixed Output Voltage, 1.5 V
VOUT = 0.5V(1 + R1/R2)
4.7µF
100kΩ
PG
16 15 14 13
VIN VIN VOUT VOUT
1 VIN
VOUT 12
2 VIN
3 VIN
ADP1741 VOUT 11
TOP VIEW
(Not to Scale) VOUT 10
4 EN
PG GND SS
567
ADJ 9
NC
8
4.7µF
R1
R2
10nF
Figure 2. ADP1741 with Adjustable Output Voltage, 0.75 V to 3.3 V
voltages ranging from 0.75 V to 3.3 V via an external divider.
The ADP1740/ADP1741 allow an external soft start capacitor
to be connected to program the startup. A digital power-good
output allows power system monitors to check the health of the
output voltage.
The ADP1740/ADP1741 are available in a 16-lead, 4 mm ×
4 mm LFCSP, making them not only very compact solutions,
but also providing excellent thermal performance for applica-
tions that require up to 2 A of output current in a small, low
profile footprint.
Rev. H
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
SS to GND
PG to GND
SENSE/ADJ to GND
Storage Temperature Range
Junction Temperature Range
Junction Temperature
Soldering Conditions
Rating
−0.3 V to +4.0 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +4.0 V
−0.3 V to VIN
−65°C to +150°C
−40°C to +125°C
150°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in
combination. The ADP1740/ADP1741 may be damaged when
junction temperature limits are exceeded. Monitoring ambient
temperature does not guarantee that the junction temperature is
within the specified temperature limits. In applications with
high power dissipation and poor PCB thermal resistance, the
maximum ambient temperature may need to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). TJ is calculated using the following formula:
TJ = TA + (PD × θJA)
The junction-to-ambient thermal resistance (θJA) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
ADP1740/ADP1741
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in × 3 in circuit
board. Refer to JEDEC JESD51-7 for detailed information about
board construction. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JEDEC JESD51-12
document, Guidelines for Reporting and Using Electronic Package
Thermal Information, states that thermal characterization
parameters are not the same as thermal resistances. ΨJB measures
the component power flowing through multiple thermal paths
rather than through a single path, as in thermal resistance (θJB).
Therefore, ΨJB thermal paths include convection from the top of
the package, as well as radiation from the package, factors that
make ΨJB more useful in real-world applications. Maximum
junction temperature (TJ) is calculated from the board temper-
ature (TB) and the power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θJA ΨJB Unit
16-Lead LFCSP with Exposed Pad
42
25.5 °C/W
ESD CAUTION
Rev. H | Page 5 of 20
5 Page 
Data Sheet
ADP1740/ADP1741
THEORY OF OPERATION
The ADP1740/ADP1741 are low dropout linear regulators
that use an advanced, proprietary architecture to provide high
power supply rejection ratio (PSRR) and excellent line and load
transient response with only a small 4.7 µF ceramic output capac-
itor. Both devices operate from a 1.6 V to 3.6 V input rail and
provide up to 2 A of output current. Supply current in shutdown
mode is typically 2 µA.
VIN
GND
PG
EN
ADP1740
UVLO
REVERSE POLARITY
PROTECTION
VOUT
SHORT-CIRCUIT
AND THERMAL
PROTECTION
PG
DETECT
0.5V
REF
SHUTDOWN
SENSE
R1
R2
0.9µA
SS
Figure 24. ADP1740 Internal Block Diagram
VIN
GND
ADP1741
REVERSE POLARITY
PROTECTION
UVLO
SHORT-CIRCUIT
AND THERMAL
PROTECTION
VOUT
The ADP1740 is available in seven fixed output voltage options
from 0.75 V to 2.5 V. The ADP1740 allows for connection of an
external soft start capacitor, which controls the output voltage
ramp during startup. The ADP1741 is an adjustable version with
an output voltage that can be set to a value from 0.75 V to 3.3 V
by an external voltage divider. Both devices are controlled by an
enable pin (EN).
SOFT START FUNCTION
For applications that require a controlled startup, the ADP1740/
ADP1741 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 µA current source charges this capacitor.
The ADP1740/ADP1741 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:
tSS = VREF × (CSS/ISS)
(1)
where:
tSS is the soft start period.
VREF is the 0.5 V reference voltage.
CSS is the soft start capacitance from SS to GND.
ISS is the current sourced from SS (0.9 µA).
When the ADP1740/ADP1741 are disabled (using the EN pin),
the soft start capacitor is discharged to GND through an
internal 100 Ω resistor.
2.50
2.25
EN
2.00
1.75
1nF
1.50
PG 0.5V
REF
PG
DETECT
EN SHUTDOWN
ADJ
0.9µA
SS
1.25
4.7nF
1.00
10nF
0.75
0.50
0.25
Figure 25. ADP1741 Internal Block Diagram
Internally, the ADP1740/ADP1741 consist of a reference,
an error amplifier, a feedback voltage divider, and a PMOS
pass transistor. Output current is delivered via the PMOS pass
transistor, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the feed-
back voltage is lower than the reference voltage, the gate of the
PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to pass and decreasing the
output voltage.
0
0 2 4 6 8 10
TIME (ms)
Figure 26. VOUT Ramp-Up with External Soft Start Capacitor
Rev. H | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADP1740.PDF ] | |
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