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PDF ADP5310 Data sheet ( Hoja de datos )
| Número de pieza | ADP5310 | |
| Descripción | Integrated Ultralow Power Solution | |
| Fabricantes | Analog Devices | |
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Data Sheet
3-Channel, Integrated Ultralow Power Solution
with Dual Buck Regulators and Load Switch
ADP5310
FEATURES
Wide input voltage range: 2.7 V to 15.0 V
700 nA quiescent current when EN1 = SYNC/MODE = low
±1.5% output accuracy over full temperature range in PWM mode
600 kHz (or 1.2 MHz) switching frequency with optional
synchronization input from 400 kHz to 1.4 MHz
Channel 1: 800 mA buck regulator
Automatic PSM/PWM or forced PWM mode via factory fuse
100% duty cycle operation mode
Adjustable/fixed output options via factory fuse
Power-good flag
Channel 2: ultralow power buck regulator
Selectable hysteresis or PWM operation mode
Output current up to 50 mA in hysteresis mode, 300 mA in
PWM mode with 100% duty cycle operation mode
Low noise at 0.8 V reference in PWM mode
Adjustable/fixed output voltage options via factory fuse
Channel 3: high-side load switch
Low RDS(ON) of 494 mΩ at VOUT3 = 2.5 V
Quick output discharge (QOD) option
UVLO, OCP, and TSD protection
16-lead TSSOP_EP package
−40°C to +125°C operational junction temperature
APPLICATIONS
Energy (gas and water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supplies
GENERAL DESCRIPTION
The ADP5310 combines dual buck regulators and one load switch
in a 16-lead TSSOP_EP package that meets demanding perfor-
mance and board space requirements. The device enables direct
connection to a wide input voltage range of 2.7 V to 15.0 V, allowing
the use of multiple alkaline/NiMH or lithium cells and other
power sources.
The buck regulator in Channel 1 uses a current mode, constant
frequency pulse-width modulation (PWM) control scheme for
excellent stability and transient performance, which provides up
to 800 mA of output current. The automatic PWM/pulse skipping
mode (PSM) control scheme achieves excellent efficiency in light
output current. A power-good signal indicates that the output
of Channel 1 is within 92% of its nominal value.
An ultralow power buck regulator is integrated in Channel 2 with
the SYNC/MODE pin to control its operation mode. When
SYNC/MODE is set to low, the buck regulator operates in hysteresis
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
TYPICAL APPLICATION CIRCUIT
FROM MCU
TO MCU
VIN =
2.7V TO 15V
C1
10µF
MLCC
EN1
PWRGD
PVIN1
ADP5310
CHANNEL 1
BUCK
REGULATOR
(800mA)
SW1
PGND1
FB1
PVIN2
NC
SYNC/
MODE
CHANNEL 2
ULTRALOW
SW2
POWER
BUCK
PGND2
REGULATOR
(50mA/300mA)
FB2
L1
4.7µH
C3
10µF
MLCC
L2
4.7µH
R1
R2
C4
10µF
MLCC
VOUT1
VOUT2
FROM MCU
EN3
CHANNEL 3 VOUT3
LOAD
SWITCH
VREG AGND
C6
1µF
C5
220nF
MLCC
VOUT3
Figure 1.
mode, which draws only 700 nA of quiescent current to regulate
the output under zero load and provides up to 50 mA of output
current. Hysteresis mode helps achieve excellent efficiency at less
than 1 mW and can work as a keep-alive power supply in a battery-
powered system. When the SYNC/MODE pin is set to high, the
buck regulator switches to a traditional constant frequency PWM
control scheme to provide low output ripple for noise sensitive
applications, and the buck regulator provides up to 300 mA of
output current in PWM mode.
Channel 3 integrates a high-side load switch that operates from
1.65 V to 5.5 V with its input connected to the output of Channel 2.
The load switch provides power domain isolation and extends
battery operation time.
Other key safety features of the ADP5310 include overcurrent
protection (OCP), thermal shutdown (TSD), and input under-
voltage lockout (UVLO). The ADP5310 is rated for the −40°C
to +125°C junction temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP5310
Data Sheet
SPECIFICATIONS
VIN = 6 V, VREG = 3.9 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 1.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
Standby Operation
Symbol
VIN
Min
2.7
IQ1
PWM Operation
UNDERVOLTAGE LOCKOUT
UVLO Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
IQ3
UVLO
VUVLO_RISING
VUVLO_FALLING
VHYS
2.15
Switching Frequency
Feedback (FB) Threshold of
Frequency Fold
SYNCHRONIZATION THRESHOLD
SYNC Clock Range
SYNC High Level Threshold
SYNC Low Level Threshold
SYNC Pulse On Time Range
EN1 and EN3
Input High Level Threshold
Input Low Level Threshold
Input Leakage Current
INTERNAL POWER GOOD
Internal Power-Good Threshold
Internal Power-Good Hysteresis
Internal Power-Good Rising Delay
fSW
VOSC_FOLD
SYNCCLOCK
SYNCCLOCK
SYNCHIGH
SYNCLOW
SYNCON
VIH
VIL
ILEAKAGE
VPWRGD(RISE)
VPWRGD(HYS)
tPWRGD_RISE
1050
525
400
800
1.2
80
1.2
88
Internal Power-Good Falling Delay
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
INTERNAL REGULATOR
VREG Output Voltage
THERMAL SHUTDOWN
Threshold
Hysteresis
tPWRGD_FALL
IPWRGD_LEAKAGE
VPWRGD_LOW
VREG 3.6
TSHDN
THYS
Typ Max
15.0
700 1850
700 3800
1.4 1.65
2.55 2.75
2.40
150
1200
600
0.3
1350
675
Unit Test Conditions/Comments
V PVIN1 and PVIN2 pins
PVIN1 and PVIN2 pins
nA −40°C ≤ TJ ≤ +85°C, EN1 =
SYNC/MODE = low
nA −40°C ≤ TJ ≤ +125°C, EN1 =
SYNC/MODE = low
mA EN1 = SYNC/MODE = high
PVIN2 pin
V
V
mV
For Channel 1 and Channel 2,
PWM mode
kHz
kHz
V
800
1400
0.4
1/fSW − 150
kHz
kHz
V
V
ns
fSW = 600 kHz
fSW = 1.2 MHz
V
0.4 V
300 nA
92 96
5
16
1
10 40
50 100
%
%
Clock
cycles
µs
nA
mV
IPWRGD = 100 µA
3.9 4.2
V
135 °C
15 °C
Rev. A | Page 4 of 28
5 Page 
ADP5310
100
90
80
70
60
50
40
30
VIN = 5V
20 VIN = 7.2V
VIN = 9V
10 VIN = 12V
VIN = 15V
0
0 100 200 300 400 500 600 700 800
LOAD CURRENT (mA)
Figure 10. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 1.8 V
100
90
80
70
60
50
40
30
VIN = 5V
20 VIN = 7.2V
VIN = 9V
10 VIN = 12V
VIN = 15V
0
0 100 200 300 400 500 600 700 800
LOAD CURRENT (mA)
Figure 11. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 3.3 V
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0.001
0.01
0.1 1
LOAD CURRENT (mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
10 100
Figure 12. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.2 V
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
0
100 200
300 400
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
500 600 700 800
LOAD CURRENT (mA)
Figure 13. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 2.5 V
100
90
80
70
60
50
40
30
20 VIN = 7.2V
VIN = 9V
10 VIN = 12V
VIN = 15V
0
0 100 200 300 400 500 600 700 800
LOAD CURRENT (mA)
Figure 14. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 5 V
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
0.001
0.01 0.1
1
LOAD CURRENT (mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
10 100
Figure 15. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.8 V
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADP5310.PDF ] | |
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