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ADP5134 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADP5134은 전자 산업 및 응용 분야에서
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부품번호 ADP5134 기능
기능 1200 mA Buck Regulators and Two 300 mA LDO Regulators
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ADP5134 데이터시트, 핀배열, 회로
Data Sheet
Dual 3 MHz, 1200 mA Buck Regulators and Two 300 mA LDO
Regulators With Precision Enable and Power-Good Output
ADP5134
FEATURES
Main input voltage range of 2.5 V to 5.5 V
Two 1200 mA buck regulators and two 300 mA LDO regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy of ±1.8%
Factory programmable or external adjustable VOUTx
Precision enable pins for easier power sequencing
Factory selectable power-good pin
3 MHz buck operation with forced PWM and automatic
PWM/PSM modes
BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V
LDO1/LDO2: output voltage range from 0.8 V to 5.2 V
LDO1/LDO2: input voltage range from 1.7 V to 5.5 V
LDO1/LDO2: high PSRR and low output noise
APPLICATIONS
Power for processors, application specific integrated circuits
(ASICs), field programmable gate arrays (FPGAs), and
radio frequency (RF) chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
The ADP5134 combines two high performance buck regulators
and two low dropout (LDO) regulators. It is available in a 24-lead
4 mm × 4 mm LFCSP.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced pulse-width modulation (PWM) mode. When the MODE
pin is set to low, the buck regulators operate in PWM mode
when the load is above a predefined threshold. When the load
current falls below a predefined threshold, the regulator operates
in power save mode (PSM), improving the light load efficiency.
The two buck regulators operate out of phase to reduce the input
capacitor requirement. The low quiescent current, low dropout
voltage, and wide input voltage range of the ADP5134 LDO
regulators extend the battery life of portable devices. The
ADP5134 LDO regulators maintain power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage of 500 mV.
VIN
2.5V TO
5.5V
VINLDO1
1.7V TO
5.5V
VINLDO2
1.7V TO
5.5V
TYPICAL APPLICATION CIRCUIT
C1
4.7µF
VIN1
16
ON EN1
OFF
12
BUCK1
1.2A
C3
4.7µF
ON
OFF
VIN2
3
EN2
7
C5
0.1µF
C6
1µF
ON
OFF
AVIN
17
VIN3
21
EN3
22
C8
1µF
ON
OFF
VIN4
23
EN4
2
MODE
BUCK2
1.2A
HOUSEKEEPING
LDO1
300mA
LDO2
300mA
VOUT1
10
SW1
15
FB1
11
PGND1
14
MODE
13
VOUT2
9
SW2
4
FB2
8
PGND2
5
L1 1µH
R1
R2
C2
10µF
PWM
PSM/PWM
L2 1µH
R3
R4
C4
10µF
VOUT3
20
FB3
19
R5
R6
VOUT4
24
1 FB4
R7
R8
C7
1µF
C9
1µF
POWER GOOD
PG
6
ADP5134
18
AGND
Figure 1.
VDDIO
R1
100kΩ
Regulators in the ADP5134 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version or factory programmable to a wide range
of preset values in the fixed voltage version.
Table 1. Family Models
Model
ADP5023
ADP5024
ADP5034
Channels
2 Bucks, 1 LDO
2 Bucks, 1 LDO
2 Bucks, 2 LDOs
ADP5037
ADP5033
ADP5040
ADP5041
2 Bucks, 2 LDOs
2 Bucks, 2 LDOs
with 2 ENx pins
1 Bucks, 2 LDOs
1 Bucks, 2 LDOs
with supervisory
circuit, watchdog
function, and
manual reset
Maximum
Current
800 mA, 300 mA
1.2 A, 300 mA
1.2 A, 300 mA
800 mA, 300 mA
800 mA, 300 mA
1.2 A, 300 mA
1.2 A, 300 mA
Package
LFCSP (CP-24-10)
LFCSP (CP-24-10)
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
WLCSP (CB-16-8)
LFCSP (CP-20-10)
LFCSP (CP-20-10)
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5134 pdf, 반도체, 판매, 대치품
Data Sheet
ADP5134
SPECIFICATIONS
GENERAL SPECIFICATIONS
VAVIN = VVIN1 = VVIN2 = 2.5 V to 5.5 V, VVIN3 = VVIN4 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and
TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
INPUT VOLTAGE RANGE
VAVIN, VVIN1,
VVIN2
2.5 5.5 V
THERMAL SHUTDOWN
Threshold
TSSD TJ rising
150 °C
Hysteresis
TSSD-HYS
20 °C
START-UP TIME1
BUCK1
tSTART1
650 µs
BUCK2
tSTART2
750 µs
LDO1, LDO2 (Fast Soft Start)
tSTART3
650 µs
LDO1, LDO2 (Slow Soft Start)
tSTART4
900 µs
START-UP TIME, BUCK2 First
BUCK2
tSTART5
750 µs
BUCK1
tSTART6
300 µs
LDO1, LDO2 (Fast Soft Start)
tSTART7
300 µs
LDO1, LDO2 (Slow Soft Start)
tSTART8
600 µs
SHUTDOWN CONTROL
All ENx pins below VIL_EN level to achive ISHUTDOWN
Level High
VIH_EN
TJ = −40°C to +85°C
0.9 V
Level Low
VIL_EN
0.35 V
PRECISION ENABLE PINS (ENx)
Regulator(s) activation/deactivation thresholds
Analog Activation Threshold
VENR
Device out of shutdown (VENx > VIH_EN)
0.94 0.97 1
V
Hysteresis (Regulator Deactivation) VENH
80 mV
Input Leakage Current
VI-LEAKAGE
0.05 1
µA
POWER-GOOD PIN (PG)
Monitors VOUT falling out of regulation
Power-Good Falling Threshold
VPGLOW
At VOUT
90 %
Power-Good Rising Threshold
VPGHYS
At VOUT
91 94 97 %
Power-Good Delay
tPGDLY
15 µs
Power-Good Leakage Current
IPGIQ
VPG = VIN
1 µA
Power-Good Output Voltage Low
VPGOL
Load current (ILOADx) = 1 mA
0.02 0.15 V
MODE PIN
Level High
VIH_MOD
1.1 V
Level Low
VIL_MOD
0.4 V
INPUT CURRENT
All Channels Enabled
ISTBY-NOSW
No load, no buck switching
113 182 µA
All Channels Disabled
ISHUTDOWN
TJ = −40°C to +85°C
0.3 1
µA
VIN1 UNDERVOLTAGE LOCKOUT
Low UVLO Input Voltage Rising
UVLOVIN1RISE
2.45 V
Low UVLO Input Voltage Falling
UVLOVIN1FALL
1.95 V
1 Start-up time is defined as the time from EN1 = EN2 = EN3 = EN4 at 0 V to VAVIN to VOUT1, VOUT2, VOUT3, and VOUT4 reaching 90% of their nominal level. Start-up
times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 28

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ADP5134 전자부품, 판매, 대치품
ADP5134
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVIN to AGND
VIN1, VIN2 to AVIN
PGND1, PGND2 to AGND
VIN3, VIN4, VOUT1, VOUT2, FB1, FB2,
FB3, FB4, EN1, EN2, EN3, EN4,
MODE, PG to AGND
VOUT3 to AGND
VOUT4 to AGND
SW1 to PGND1
SW2 to PGND2
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (AVIN + 0.3 V)
−0.3 V to (VIN3 + 0.3 V)
−0.3 V to (VIN4 + 0.3 V)
−0.3 V to (VIN1 + 0.3 V)
−0.3 V to (VIN2 + 0.3 V)
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Considerations section.
Data Sheet
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
24-Lead, 0.5 mm Pitch LFCSP
θJA θJC Unit
35 3 °C/W
ESD CAUTION
Rev. 0 | Page 6 of 28

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