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기능 Micro PMU
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ADP5041 데이터시트, 핀배열, 회로
Data Sheet
Micro PMU with 1.2 A Buck, Two 300 mA LDOs,
Supervisory, Watchdog, and Manual Reset
ADP5041
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with externally adjustable
threshold monitoring
Guaranteed reset output valid to VAVIN = 1 V
Manual reset input
Watchdog refresh input
Buck key specifications
Output voltage range: 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM mode
100% duty cycle low dropout mode
LDOs key specifications
Output voltage range: 0.8 V to 5.2 V
Low input supply voltage from 1.7 V to 5.5 V
Stable with 2.2 μF ceramic output capacitors
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5041 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes
board space.
When the MODE pin is set to logic high, the buck regulator
operates in forced PWM mode. When the MODE pin is set to
logic low, the buck regulator operates in PWM mode when the
load is around the nominal value. When the load current falls
below a predefined threshold, the regulator operates in power
save mode (PSM), improving the light load efficiency. The low
quiescent current, low dropout voltage, and wide input voltage
FUNCTIONAL BLOCK DIAGRAM
RFILT = 30
AVIN
VIN1
=
2.3V TO
5.5V
VIN2 = 1.7V
TO 5.5V
C1
4.7µF
ON
OFF
VBIAS
VIN1
BUCK
EN_BK
EN1
C2
1µF
ON
OFF
VIN2
EN2
MR
LDO1
(DIGITAL)
EN_LDO1
VBIAS
SUPERVISOR
ON
OFF
EN3
VIN3 = 1.7V
TO 5.5V
VIN3
C3
1µF
EN_LDO2
LDO2
(ANALOG)
AGND
VOUT1
SW
FB1
R2
PGND
L1
1µH
R1
VOUT1 AT
1.2A
C6
10µF
MODE
VOUT2
FB2
R4
FPWM
PSM/PWM
R3
C5
2.2µF
VOUT2 AT
300mA
nRSTO
WDI
VTHR
R4
µP
R5
VOUT3
FB3
R3
R7
VOUT3 AT
300mA
C6
2.2µF
Figure 1.
range of the ADP5041 LDOs extend the battery life of portable
devices. The ADP5041 LDOs maintain a power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator in the ADP5041 is activated by a high level on
the respective enable pin. The output voltages of the regulators
and the reset threshold are programmed through external resistor
dividers to address a variety of applications. The ADP5041
contains supervisory circuits that monitor power supply voltage
levels and code execution integrity in microprocessor-based
systems. They also provide power-on reset signals. An on-chip
watchdog timer can reset the microprocessor if it fails to strobe
within a preset timeout period.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.




ADP5041 pdf, 반도체, 판매, 대치품
Data Sheet
ADP5041
SPECIFICATIONS
GENERAL SPECIFICATIONS
AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = −40°C to +125°C for minimum/maximum
specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
AVIN UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Option 0
Option 1
Input Voltage Falling
Option 0
Option 1
SHUTDOWN CURRENT
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
START-UP TIME1
Buck
LDO1, LDO2
ENx, WDI, MODE, MR INPUTS
Input Logic High
Input Logic Low
Input Leakage Current
OPEN-DRAIN OUTPUT
nRSTO Output Voltage
Open-Drain Reset Output Leakage
Current
Symbol
UVLOAVIN
UVLOAVINRISE
Test Conditions/Comments
UVLOAVINFALL
IGND-SD
TSSD
TSSD-HYS
tSTART1
tSTART2
VIH
VIL
VI-LEAKAGE
VOL1V
VOL1V2
VOL2V7
VOL4V5
ENx = GND
TJ rising
VOUT2, VOUT3 = 3.3 V
2.5 V ≤ AVIN ≤ 5.5 V
2.5 V ≤ AVIN ≤ 5.5 V
ENx = AVIN or GND
AVIN ≥ 1.0 V, ISINK = 50 µA
AVIN ≥ 1.2 V, ISINK = 100 µA
AVIN ≥ 2.7 V, ISINK = 1.2 mA
AVIN ≥ 4.5 V, ISINK = 3.2 mA
AVIN = 5.5 V
Min Typ Max Unit
2.275 V
3.9 V
1.95
3.1
0.1 2
150
20
V
V
µA
°C
°C
250 µs
85 µs
1.2
0.4
0.05 1
V
V
µA
0.3 V
0.3 V
0.3 V
0.4 V
1 µA
1 Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to VAVIN to the moment VOUT1, VOUT2, and VOUT3 are reaching 90% of
their nominal levels. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for
more information.
SUPERVISORY SPECIFICATIONS
AVIN, VIN1 = 2.3 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 2.
Parameter
SUPPLY
Supply Current (Supervisory Circuit Only)
Min
THRESHOLD VOLTAGE
RESET TIMEOUT PERIOD
Option 0
Option 1
VCC TO RESET DELAY (tRD)
0.495
24
160
Typ
45
43
0.500
30
200
80
Max
55
52
0.505
36
240
Unit Test Conditions/Comments
µA AVIN = VIN1 = EN1 = EN2 = EN3 =
5.5 V
µA AVIN = VIN1 = EN1 = EN2 = EN3 =
3.6 V
V
ms
ms
µs VIN falling at 1 mV/µs
Rev. 0 | Page 3 of 40

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ADP5041 전자부품, 판매, 대치품
ADP5041
Data Sheet
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter
INPUT CAPACITANCE (BUCK)1
OUTPUT CAPACITANCE (BUCK)2
INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2)
CAPACITOR ESR
Symbol
CMIN1
CMIN2
CMIN34
RESR
Test Conditions/Comments
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
TJ = −40°C to +125°C
Min
4.7
7
0.70
0.001
Typ
Max
40
40
1
Unit
µF
µF
µF
Ω
1 The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas
Y5V and Z5U capacitors are not recommended for use with the buck.
2 The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application
must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas
Y5V and Z5U capacitors are not recommended for use with the buck.
3 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
whereas Y5V and Z5U capacitors are not recommended for use with LDOs.
Rev. 0 | Page 6 of 40

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