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ADP1974 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ADP1974
기능 Synchronous PWM Controller
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ADP1974 데이터시트, 핀배열, 회로
Data Sheet
Bidirectional, Synchronous PWM Controller
for Battery Test and Formation
ADP1974
FEATURES
GENERAL DESCRIPTION
Input voltage range: 6 V to 60 V
On-board 5 V linear regulator
Buck/charge or boost/discharge mode
High PWM linearity with internal 4 V p-p PWM ramp voltage
FAULT and COMP input compatible with AD8450/AD8451
Programmable dead time control
Adjustable frequency from 50 kHz to 300 kHz
Synchronization output or input with adjustable phase shift
Programmable maximum duty cycle
Programmable soft start
Peak hiccup current-limit protection
Pin-compatible with ADP1972 (asynchronous version)
TSD protection
16-lead TSSOP
APPLICATIONS
Single and multicell battery formation and testing
High efficiency battery test systems with recycle capability
Battery conditioning (charging and discharging) systems
Compatible with AD8450/AD8451 constant voltage (CV) and
constant current (CC) analog front end error amplifier
The ADP1974 is a constant frequency, voltage mode, synchronous,
pulse-width modulation (PWM) controller for bidirectional dc-to-
dc applications. The ADP1974 is designed for use in battery testing,
formation, and conditioning applications with an external, high
voltage field effect transistor (FET) half bridge driver, and an
external control device such as the AD8450/AD8451. The device
operates as a buck converter in battery charge mode and as a boost
converter in discharge mode to recycle energy to the input bus.
The ADP1974 high voltage VIN supply pin can withstand a
maximum operating voltage of 60 V and reduces the need for
additional system supply voltages. The ADP1974 has integrated
features such as precision enable, internal and external
synchronization control with programmable phase shift,
programmable maximum duty cycle, dead time control, and peak
hiccup current-limit protection. Additional protection features
include soft start to limit input inrush current during startup,
precision enable, and thermal shutdown (TSD). The ADP1974
also has a COMP pin to provide external control of the PWM
duty cycle and a FAULT pin that can disable the DH and DL
outputs. These functions are compatible with the AD8450/AD8451
analog front-end (AFE) error amplifiers.
The ADP1974 is available in a 16-lead TSSOP package and is
pin-compatible with the ADP1972.
TYPICAL APPLICATION CIRCUIT
BATTERY CHARGER SYSTEM CONTROL
+24V
VOLTAGE CURRENT
CHARGE/
SETPOINT SETPOINT DISCHARGE
ON/OFF
LOOP
COMPENSATION
ISET MODE
VCTRL
VSET
FAULT
AD8450
BVP0 BVN0 ISVN ISVP
+––+
VIN
VREG
SYNC
SCFG
EN ADP1974
MODE
DH
COMP
FAULT
FREQ
DMAX
GND
DL
CL
DT
SS
HV
MOSFET
DRIVER
ADuM7223
+24V RECYLCING DC BUS
NOTES
1. THE AD8450 AND ADuM7223 ARE SIMPLIFIED REPRESENTATIONS.
Figure 1.
Rev. 0
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ADP1974 pdf, 반도체, 판매, 대치품
Data Sheet
ADP1974
SPECIFICATIONS
VIN = 24 V and specifications valid for TJ = −40°C to +125°C, unless otherwise specified. Typical values are at TA = 25°C. All limits at
temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Table 1.
Parameter
INPUT VOLTAGE (VIN)
Voltage Range
VIN Supply Current
VIN Shutdown Current
UVLO Threshold Rising
UVLO Threshold Falling
SOFT START (SS)
SS Pin Current
SS Threshold Rising
SS Threshold Falling
End of Soft Start
PWM CONTROL
FREQ
Frequency Range
Oscillator Frequency
FREQ Pin Voltage
SYNC Output (Internal Frequency Control)
Internal SYNC Range
SYNC Output Clock Duty Cycle
SYNC Sink Resistance
SYNC Input (External Frequency Control)
External SYNC Range
SYNC Pull-Down Resistor
Maximum SYNC Pin Voltage
SYNC Threshold Rising
SYNC Threshold Falling
Minimum Pulse Width
SCFG
SCFG High Threshold Rising
SCFG High Threshold Falling
SCFG Low Threshold Rising
SCFG Low Threshold Falling
SCFG Pin Current
DMAX
Maximum Internal Duty Cycle
DMAX Setting Current
DMAX and SCFG Current Matching1
COMP
COMP Pin Input Voltage Range
Internal Peak-to-Peak Ramp Voltage
Maximum Internal Ramp Voltage
Minimum Internal Ramp Voltage
DT
DT Pin Current
Maximum DT Programming Voltage
Symbol
VIN
IVIN
ISHDN
ISS
fSET
fOSC
VFREQ
fSET
RSYNC
fSYNC
VSYNC
VSCFG
IISCFG
IDMAX
VCOMP
V p-p
IDT
VDT
Test Conditions/Comments
RFREQ = 100 kΩ, VSS = 0 V, SYNC floating,
FAULT = low, EN = high
VEN = 0 V
VIN rising
VIN falling
VSS = 0 V
Switching enable threshold
Switching disable threshold
Asynchronous to synchronous threshold
RFREQ = 33.2 kΩ to 200 kΩ
RFREQ = 100 kΩ
RFREQ = 100 kΩ
VSCFG ≥ 4.53 V or SCFG pin floating
For SYNC output
VSCFG = VVREG, RFREQ = 100 kΩ
VSCFG = 5 V, ISYNC = 10 mA
VSCFG < 4.25 V
For SYNC input clock
SYNC set to input
SYNC set to output
Programmable phase shift above threshold
No phase shift
RFREQ = 100 kΩ, VSCFG = GND
VCOMP, VDMAX, VSS, and VSCFG = 5 V
VDMAX = 0 V, RFREQ = 100 kΩ
RFREQ = 100 kΩ, VDT = GND
Min Typ Max Unit
6 60 V
1.5 2.5 mA
15 70
5.71 6
5.1 5.34
μA
V
V
45
6 μA
0.52 0.65 V
0.4 0.5
V
4.4 4.5 4.6 V
50 300 kHz
90 100 110 kHz
1.2 1.252 1.3 V
50
40 50
10
300 kHz
60 %
20 Ω
50 300 kHz
0.5 1
1.5 MΩ
5.5 V
1.2 1.5 V
0.7 1.05
V
100 ns
4.53
4.25 4.51
0.52
0.4 0.5
9.5 11
4.7 V
V
0.65 V
V
12.5 μA
97
9.5 11
%
12.5 μA
10 %
0
4
4.5
0.45 0.5
5.0 V
V p-p
V
0.55 V
20 22 μA
3.5 V
Rev. 0 | Page 3 of 19

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ADP1974 전자부품, 판매, 대치품
ADP1974
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
DL 1
DH 2
VREG 3
VIN 4
EN 5
MODE 6
SYNC 7
FAULT 8
16 CL
15 GND
ADP1974
TOP VIEW
(Not to Scale)
14 DT
13 SCFG
12 FREQ
11 DMAX
10 SS
9 COMP
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 DL
Logic Drive Output for the External Low-Side MOSFET Driver.
2 DH
Logic Drive Output for the External High-Side MOSFET Driver.
3
VREG
Internal Voltage Regulator Output and Internal Bias Supply. A bypass capacitance of 1 μF or greater from this pin
to ground is required.
4 VIN
High Input Voltage Supply Pin (6 V to 60 V). Bypass this pin with a 4.7 μF capacitor to ground.
5 EN
Logic Enable Input. Drive EN logic low to shut down the device. Drive EN logic high to turn on the device.
6
MODE
Mode Select. Drive MODE logic low to place the device in boost (recycle) mode. Drive MODE logic high to place
the device in buck (charge) mode of operation. The MODE status is sampled at EN rising or FAULT falling (see the
Operating Modes section).
7
SYNC
Synchronization Pin. This pin is configured as an input (slave mode) with SCFG < 4.51 V to synchronize the ADP1974
to an external clock. This pin is an open-collector driver output with SCFG > 4.53 V (or SCFG connected to VREG).
When configured as an output, SYNC is used to synchronize with other channels; a 10 kΩ resistor to VREG can be
used as a pull-up.
8
FAULT
Fault Input Pin. Drive FAULT low to disable the DL and DH drivers in the event of a fault. Drive FAULT high to enable
the DL and DH drivers. FAULT can also reset the mode of operation as described in the Operating Modes section.
This pin was designed to interface with the overcurrent protection (OCP) or overvoltage protection (OVP) fault
condition on the AD8450/AD8451.
9
COMP
PWM Modulator Input. This pin interfaces with an error amplifier output signal from the AD8450/AD8451. The
signal on this pin is compared internally to the linear ramp to produce the PWM signal. Do not leave this pin
floating; see the External COMP Control section for additional details.
10 SS
Soft Start Control Pin. A capacitor connected from SS to ground sets the soft start ramp time. Soft start controls the
DL and DL duty cycle during power-up to reduce the inrush current. Drive SS below 0.5 V to disable switching of DL
and DH. During soft start, the ADP1974 operates in pseudosynchronous mode (see the Soft Start section).
11
DMAX
Maximum Duty Cycle Input. Connect an external resistor to ground to set the maximum duty cycle. If the 97%
internal maximum duty cycle is sufficient for the application, tie this pin to VREG. If DMAX is left floating, this pin
is internally pulled up to VREG.
12 FREQ Frequency Set Pin. Connect an external resistor between this pin and ground to set the frequency between 50 kHz
and 300 kHz. When the ADP1974 is synchronized to an external clock (slave mode), set the slave frequency to 90%
of the master frequency by multiplying the master RFREQ value times 1.11.
13 SCFG Synchronization Configuration Input. Drive VSCFG ≥ 4.53 V (typical) to configure SYNC as an output clock signal.
Drive VSCFG < 4.51 V (typical) to configure SYNC as an input. Connect a resistor to ground with 0.52 V < VSCFG < 4.53 V
(typical) to introduce a phase shift to the synchronized clock. Drive VSCFG ≤ 0.5 V (typical) to configure SYNC as an
input with no phase shift. If SCFG is left floating, the SYNC pin is internally tied to VREG, and SYNC is configured as
an output.
14 DT
Dead Time Programming Pin. Connect an external resistor between this pin and ground to set the dead time.
Do not leave this pin floating.
15 GND
Power and Analog Ground Pin.
16 CL
Current-Limit Programming Pin. Connect a current sense resistor in series with the low-side FET source to measure
the peak current in the inductor. The current-limit thresholds can operate with a 20 kΩ resistor as described in the
Peak Current-Limit Hiccup Implementation section.
Rev. 0 | Page 6 of 19

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