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PDF ADP1853 Data sheet ( Hoja de datos )
| Número de pieza | ADP1853 | |
| Descripción | Step-Down DC-to-DC Controller | |
| Fabricantes | Analog Devices | |
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Data Sheet
Synchronous, Step-Down DC-to-DC Controller with
Voltage Tracking and Synchronization
ADP1853
FEATURES
Input voltage range: 2.75 V to 20 V
Output voltage range: 0.6 V to 90% VIN
Maximum output current of more than 25 A
Current mode architecture with current sense input
Configurable to voltage mode
±1% output voltage accuracy over temperature
Voltage tracking input
Programmable frequency: 200 kHz to 1.5 MHz
Synchronization input
Internal clock output
Power saving mode at light load
Precision enable input
Power good with internal pull-up resistor
Adjustable soft start
Programmable current sense gain
Integrated bootstrap diode
Starts into a precharged load
Externally adjustable slope compensation
Suitable for any output capacitor
Overvoltage and overcurrent-limit protection
Thermal overload protection
Input undervoltage lockout (UVLO)
Available in 20-lead, 4 mm × 4 mm LFCSP
Supported by ADIsimPower™ design tool
APPLICATIONS
Intermediate bus and POL systems requiring sequencing and
tracking, including
Telecom base station and networking
Industrial and Instrumentation
Medical and healthcare
GENERAL DESCRIPTION
The ADP1853 is a wide range input, dc-to-dc, synchronous
buck controller capable of running from commonly used 3.3 V
to 12 V (up to 20 V) voltage inputs. The device nominally
operates in current mode with valley current sensing providing
the fastest step response for digital loads. It can also be
configured as a voltage mode controller with low noise and
crosstalk for sensitive loads.
The ADP1853 can be used as a master synchronization clock
for the power system and for convenient synchronization
between controllers. The CLKOUT signal can synchronize
other devices in the ADP185x family such that slave devices
are phase-shifted from the master to reduce the input ripple
current, improve EMI, and reduce the size of the input bulk
capacitance. The ADP1853 can also be configured as a slave
device for current sharing. Additionally, the ADP1853 includes
accurate tracking, precision enable, and power good functions
for sequencing. The ADP1853 provides a high speed, high peak
current gate driving capability to enable energy efficient power
conversion. The device can be configured to operate in power
saving mode by skipping pulses, reducing switching losses and
improving efficiency at light load and standby conditions.
The accurate current limit allows design within a narrower
range of tolerances and can reduce overall converter size and
cost. The ADP1853 can regulate down to 0.6 V output using a
high accuracy reference with ±1% tolerance over the
temperature range from −40°C to 125°C.
With a wide range input voltage, the ADP1853 is designed to
provide the designer with maximum flexibility for use in a
variety of system configurations; loop compensation, soft start,
frequency setting, power saving mode, current limit, and
current sense gain can all be programmed using external
components. In addition, the external RAMP resistor allows
choosing optimal slope and VIN feedforward in both current
and voltage mode for excellent line rejection. The linear
regulator and the boot strap diode for the high-side driver are
internal.
Protection features include undervoltage lock out, overvoltage,
overcurrent/short circuit, and overtemperature.
VMA
HI
LO
RRAMP
RAMP
VIN
EN
TRK
VCCO
DH
BST
SW
CS
ILIM
ADP1853
DL
SYNC
FREQ
PGND
FB
SS COMP
VIN
M1
L
M2
RCSG
VOUT
AGND
PGOOD
CLKOUT
Figure 1. Typical Operation Circuit
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP1853
Parameter
LOGIC INPUTS
EN
EN Hysteresis
EN Input Leakage Current
SYNC Logic Input Low
SYNC Logic Input High
SYNC Input Pull-Down Resistance
GATE DRIVERS
DH Rise Time
DH Fall Time
DL Rise Time
DL Fall Time
DH to DL Dead Time
DH or DL Driver RON, Sourcing
Current1
Symbol
IEN
RSYNC
RON_SOURCE
DH or DL Driver RON, Tempco
DH or DL Driver RON, Sinking
Current1
TCRON
RON_SINK
DH Maximum Duty Cycle1
DH Maximum Duty Cycle1
Minimum DH On Time
Minimum DH Off Time
Minimum DL On Time
COMP VOLTAGE RANGE
COMP Pulse Skip Threshold
COMP Clamp High Voltage
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
OVERVOLTAGE AND POWER GOOD
THRESHOLDS
FB Overvoltage Threshold
FB Overvoltage Hysteresis
FB Undervoltage Threshold
FB Undervoltage Hysteresis
TRK INPUT VOLTAGE RANGE1
FB TO TRK OFFSET VOLTAGE
SOFT START
SS Output Current
SS Pull-Down Resistor
FB to SS offset
VCOMP,THRES
VCOMP,HIGH
TTMSD
VOV
VUV
ISS
Test Conditions/Comments
EN rising
VIN = 2.75 V to 20 V
CDH = 3 nF, VBST − VSW = 5 V
CDH = 3 nF, VBST − VSW = 5 V
CDL = 3 nF
CDL = 3 nF
External 3 nF is connected to DH and DL
Sourcing 2 A with a 100 ns pulse
Sourcing 1 A with a 100 ns pulse, VIN = 3 V
VIN = 3 V or 12 V
Sinking 2 A with a 100 ns pulse
Sinking 1 A with a 100 ns pulse, VIN = 3 V
fOSC = 300 kHz
fOSC = 1500 kHz
fOSC = 200 kHz to 1500 kHz
fOSC = 200 kHz to 1500 kHz
fOSC = 200 kHz to 1500 kHz
In pulse skip mode (PSM)
VFB rising
VFB falling
TRK = 0.1 V to 0.57 V; offset = VFB − VTRK
During startup
During a fault condition
VSS = 0.1 V to 0.6 V; offset = VFB − VSS
Data Sheet
Min Typ Max Unit
0.57 0.63 0.68 V
0.03 V
1 200 nA
1.3 V
1.9 V
1 MΩ
16 ns
14 ns
16 ns
14 ns
25 ns
2Ω
2.3 Ω
0.3 %/oC
1.5 Ω
2
90
50
Ω
%
%
85 ns
345 ns
295 ns
0.9
2.2
V
V
155 °C
20 °C
0.630
0.525
0
−10
4.6
−10
0.65
18
0.55
15
0
6.5
3
0.670
0.575
5
+10
8.4
+10
V
mV
V
mV
V
mV
µA
kΩ
mV
Rev. A | Page 4 of 28
5 Page 
ADP1853
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
70
60
50
40
30
20
10 PULSE SKIP
FORCED PWM
0
0.1 1 10 100
LOAD (A)
Figure 4. Efficiency Plot
12 VIN to 3.3 VOUT, 300 kHz, see Figure 36 for Circuit
Data Sheet
100
90
80
70
60
50
40
30
20
10 PULSE SKIP
FORCED PWM
0
0.1 1 10 100
LOAD (A)
Figure 7. Efficiency Plot
15 VIN to 5 VOUT, 600 kHz, see Figure 35 for Circuit
LOAD
CURRENT
4
2
VOUT_AC
LOAD
CURRENT
4
VOUT_AC
2
CH2 200mV BW M 100µs 5.0MS/s A CH4
CH4 10A Ω BW 200ns/pt
Figure 5. 10 A to 20 A Load Step,
12 VIN to 3.3 VOUT, 300 kHz, Current Mode
14.2A
CH2 200mV BW M 100µs 5.0MS/s A CH4
CH4 10A Ω BW 200ns/pt
Figure 8. 10 A to 20 A Load Step,
12 VIN to 3.3 VOUT, 300 kHz, Voltage Mode
14.2A
VIN
1
VOUT_AC
2
CH1 5V
CH2 100mV
BW
BW
M 100µs 250MS/s A CH1
4ns/pt
Figure 6. 9 V to 15 V Line Step,
3.3 VOUT, 15 A Load, Current Mode
12.6V
VIN
1
VOUT_AC
2
CH1 5V
CH2 100mV
BW
BW
M 100µs 250MS/s A CH1
4ns/pt
Figure 9. 9 V to 15 V Line Step,
3.3 VOUT, 15 A Load, Voltage Mode
12.6V
Rev. A | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet ADP1853.PDF ] | |
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