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부품번호 ADP5302 기능
기능 Ultralow Power Step-Down Regulator
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ADP5302 데이터시트, 핀배열, 회로
Data Sheet
50 mA/500 mA, Ultralow Power Step-Down
Regulator With Battery Voltage Monitor
ADP5302
FEATURES
Input supply voltage range: 2.15 V to 6.50 V
Operates down to 2.00 V
Ultralow 240 nA quiescent current with no load
Selectable output voltages of 1.2 V to 3.6 V, or 0.8 V to 5.0 V
±1.5% output accuracy over the full temperature range in
pulse-width modulation (PWM) mode
Selectable hysteresis mode or PWM operation mode
Output current
Up to 50 mA in hysteresis mode
Up to 500 mA in PWM mode
VINOK flag to monitor input battery voltage
Ultrafast stop switching control
100% duty cycle operation mode
2 MHz switching frequency with optional synchronization
input from 1.5 MHz to 2.5 MHz
Quick output discharge (QOD) option
UVLO, OCP, and TSD protection
10-lead, 3 mm × 3 mm LFCSP package
Junction temperature: −40°C to +125°C
APPLICATIONS
Energy (gas, water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supplies
GENERAL DESCRIPTION
The ADP5302 is a high efficiency, ultralow quiescent current
step-down regulator that draws only 240 nA quiescent current
to regulate the output at no load.
The ADP5302 runs from an input voltage of 2.15 V to 6.50 V,
allowing the use of multiple alkaline or NiMH cells, Li-Ion cells,
or other power sources. The output voltage is selectable from 0.8 V
to 5.0 V by an external VID resistor and a factory fuse. The total
solution requires only four tiny external components.
The ADP5302 can operate between hysteresis mode and PWM
mode via the SYNC/MODE pin. In hysteresis mode, the regulator
achieves excellent efficiency at less than 1 mW and provides up to
50 mA of output current. In PWM mode, the regulator produces a
lower output ripple and supplies up to 500 mA of output current.
The flexible configuration capability during operation of the
device enables very efficient power management to meet both
long battery life and low system noise requirements.
TYPICAL APPLICATION CIRCUIT
VIN =
2.15V TO 6.50V
10µF
ON
OFF
PVIN
EN
ADP5302
(LFCSP-10)
SW
PGND
2.2µH
10µF
VOUT
PWM
HYS
STOP
SW
SYNC/
MODE
STOP
AGND
FB
VINOK
VID
EPAD
VID0: 1.2V VID8: 2.5V
VID1: 1.5V VID9: 2.6V
VID2: 1.8V VID10: 2.7V
VID3: 2.0V VID11: 2.8V
R0
VID4: 2.1V
VID5: 2.2V
VID12: 2.9V
VID13: 3.0V
VID6: 2.3V VID14: 3.3V
VID7: 2.4V VID15: 3.6V
Figure 1.
The ADP5302 integrates an ultralow power comparator with a
factory programmable voltage reference to monitor the input
battery voltage. The regulator runs at a 2 MHz switching
frequency in PWM mode, and the SYNC/MODE pin can be
synchronized to an external clock from 1.5 MHz to 2.5 MHz.
The ADP5302 includes an extra STOP pin that can temporarily
disable the regulator switching; in this way, a quiet system environ-
ment can be achieved to benefit the noise sensitive circuitry, which
includes data conversion, RF data transmission, and analog sensors.
Other key features in the ADP5302 include separate enabling,
QOD, and safety features, such as overcurrent protection
(OCP), thermal shutdown (TSD), and input undervoltage
lockout (UVLO).
The ADP5302 is available in a 10-lead, 3 mm × 3 mm LFCSP
package rated for the −40°C to +125°C junction temperature range.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5302 pdf, 반도체, 판매, 대치품
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
ADP5302
VINOK
VINOK_TH
PVIN
ILIM_PWM
STOP
1.2V
0.4V
FORCE SLEEP
ILIM_HYS
SLOPE
COMPENSATION
Σ
0.808V
0.8V
CONTROL
LOGIC
PWM
STANDBY
PVIN
DRIVER
–0.6A (PWM)
0A (HYS)
PVIN
DRIVER
EN
SYNC/
MODE
1.2V
0.4V
PVIN
2.06V
2.00V
1.2V
0.4V
V TO I
UVLO
BAND GAP BIAS
AND
HOUSEKEEPING
KEEP ALIVE BLOCK
SYNC
MODE
2MHz
OSC
Figure 2. Detailed Functional Block Diagram
0.8V
SOFT
START
INTERNAL
FEEDBACK
RESISTOR
DIVIDE
MODE
ADP5302
PVIN
SW
PGND
FB
VID
AGND
Rev. A | Page 3 of 22

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ADP5302 전자부품, 판매, 대치품
ADP5302
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN to PGND
SW to PGND
FB to AGND
VID to AGND
EN to AGND
VINOK to AGND
SYNC/MODE to AGND
STOP to AGND
PGND to AGND
Storage Temperate Range
Operational Junction Temperature Range
Rating
−0.3 V to +7 V
−0.3 V to PVIN + 0.3 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−65°C to +150°C
−40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. θJC is
the thermal resistance from the operating portion of the device
to the outside surface of the package (case) closest to the device
mounting area.
Table 3. Thermal Resistance
Package Type
10-Lead, 3 mm × 3 mm LFCSP
θJA
57
θJC Unit
0.86 °C/W
ESD CAUTION
Rev. A | Page 6 of 22

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