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기능 DC-to-DC Inverting Regulator
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ADP5075 데이터시트, 핀배열, 회로
Data Sheet
800 mA, DC-to-DC Inverting Regulator
ADP5075
FEATURES
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to VIN − 39 V
Integrated 800 mA main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
UVLO, OCP, OVP, and TSD protection
1.61 mm × 2.18 mm, 12-ball WLCSP
−40°C to +125°C junction temperature range
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and multiplexers
Charge coupled device (CCD) bias supplies
Optical module supplies
Radio frequency (RF) power amplifier (PA) bias
GENERAL DESCRIPTION
The ADP5075 is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the input
voltage.
The ADP5075 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5075 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The ADP5075 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown.
TYPICAL APPLICATION CIRCUIT
VIN
CIN
ON
OFF
RC
CC
CVREG
AVIN
PVIN
VREF
ADP5075 FB
EN
SS SW
COMP
SLEW
VREG SYNC/FREQ
GND
CVREF
RFB
RFT
D1
L1
VOUT
COUT
Figure 1.
Other key safety features in the ADP5075 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5075 is available in a 12-ball WLCSP and is rated for a
−40°C to +125°C junction temperature range.
Table 1. Related Devices
Device
Boost
Switch (A)
Inverter
Switch (A)
ADP5070 1.0
0.6
ADP5071 2.0
1.2
ADP5075 Not
applicable
0.8
Package
20-lead LFCSP (4 mm ×
4 mm) and 20-lead TSSOP
20-lead LFCSP (4 mm ×
4 mm) and 20-lead TSSOP
12-ball WLCSP
(1.61 mm × 2.18 mm)
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5075 pdf, 반도체, 판매, 대치품
Data Sheet
ADP5075
SPECIFICATIONS
PVIN = AVIN = 2.85 V to 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA =
25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
PVIN, AVIN (Total)
Shutdown Current
UVLO
System UVLO Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
Symbol
VIN
IQ
ISHDN
VUVLO_RISING
VUVLO_FALLING
VHYS
fSW
SYNC/FREQ Input
Input Clock Range
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
PRECISION ENABLING (EN)
High Level Threshold
Low Level Threshold
Shutdown Mode
Pull-Down Resistance
INTERNAL REGULATOR
VREG Output Voltage
INVERTING REGULATOR
Reference Voltage
Accuracy
fSYNC
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
VTH_H
VTH_L
VTH_S
REN
VREG
VREF
Feedback Voltage
Accuracy
VREF − VFB
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
Line Regulation
EA Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage
Current-Limit Threshold
Minimum On Time
Minimum Off Time
IFB
VOV
∆(VREF − VFB)/
ILOAD
∆(VREF − VFB)/
VPVIN
gM
RDS (ON)
VDS (MAX)
ILIM
Min
2.85
2.5
1.130
2.240
1.000
100
100
0.4
1.125
1.025
0.4
−0.5
−1.5
−0.5
−1.5
270
800
Typ Max
15
1.8 4.0
5 10
2.8 2.85
2.55
0.25
1.200 1.270
2.400 2.560
2.600
1.3
1.15 1.175
1.05 1.075
1.48
4.25
1.60
0.8
0.74
0.0004
+0.5
+1.5
+0.5
+1.5
0.1
0.003
300 330
330
39
880 960
60
50
Unit Test Conditions/Comments
V PVIN, AVIN
mA No switching, EN = high, PVIN = AVIN =
5V
µA No switching, EN = low, PVIN = AVIN = 5 V
AVIN
V
V
V
MHz SYNC/FREQ = low
MHz SYNC/FREQ = high (connect to VREG)
MHz
ns
ns
V
V
V
V
V Internal circuitry disabled to achieve ISHDN
MΩ
V
V
%
%
V
%
%
µA
V
%/mA
TJ = 25°C
TJ = −40°C to +125°C
TJ = 25°C
TJ = −40°C to +125°C
At the FB pin after soft start is complete
ILOAD = 5 mA to 75 mA
%/V VPVIN = 2.85 V to 14.5 V, ILOAD = 15 mA
µA/V
mΩ
V
mA
ns
ns
Rev. A | Page 3 of 18

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ADP5075 전자부품, 판매, 대치품
ADP5075
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
1 23
A
AVIN
PVIN
SW
B
VREG
SLEW
SS
C
GND SYNC/FREQ EN
D
VREF
FB COMP
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No. Mnemonic Description
A1 AVIN
System Power Supply for the ADP5075.
A2 PVIN
Power Input for the Inverting Regulator.
A3 SW
Switching Node for the Inverting Regulator.
B1 VREG
Internal Regulator Output. Connect a 1.0 µF ceramic filter capacitor between the VREG pin and GND.
B2 SLEW
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest slew
rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the slowest
slew rate (best noise performance), connect the SLEW pin to ground.
B3 SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start
time, connect a resistor between the SS pin and GND.
C1 GND
Ground.
C2 SYNC/FREQ Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To
set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency,
connect the SYNC/FREQ pin to an external clock.
C3 EN
Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the
inverting regulator output.
D1 VREF
Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and ground.
D2 FB
Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting
regulator output capacitor and VREF to program the output voltage.
D3 COMP
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and GND.
Rev. A | Page 6 of 18

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