PDF ADAU1772 Data sheet ( Hoja de datos )

Número de pieza	ADAU1772
Descripción	Four ADC / Two DAC Low Power Codec
Fabricantes	Analog Devices
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Data Sheet Four ADC, Two DAC Low Power Codec with Audio Processor ADAU1772 FEATURES Programmable audio processing engine 192 kHz processing path Biquad filters, limiters, volume controls, mixing Low latency, 24-bit ADCs and DACs 102 dB SNR (signal through PGA and ADC with A-weighted filter) 107 dB combined SNR (signal through DAC and headphone with A-weighted filter) Serial port sample rates from 8 kHz to 192 kHz 38 μs analog-to-analog latency 4 single-ended analog inputs—configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output—single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full-duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital I/O of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V Low power (15 mW for typical noise cancelling solution) I2C and SPI control interfaces, self-boot from I2C EEPROM 7 MP pins supporting dual stereo digital microphone inputs, stereo PDM output, mute, DSP bypass, push-button volume controls, and parameter bank switching APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1772 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, a crystal, and an EEPROM for booting, the ADAU1772 provides a complete headset solution. FUNCTIONAL BLOCK DIAGRAM MICBIAS0 MICBIAS1 AIN0REF AIN0 AIN1REF AIN1 DMIC0_1/MP4 DMIC2_3/MP5 AIN2REF AIN2 AIN3REF AIN3 CM MICROPHONE BIAS GENERATORS PGA ADC MODULATOR PGA ADC MODULATOR DIGITAL MICROPHONE INPUTS PGA ADC MODULATOR PGA ADC MODULATOR POWER MANAGEMENT LDO REGULATOR ADC DECIMATOR ADC DECIMATOR INPUT/OUTPUT SIGNAL ROUTING ADC DECIMATOR ADC DECIMATOR DSP CORE: BIQUAD FILTERS, LIMITERS, VOLUME CONTROLS, MIXING ADAU1772 PLL CLOCK OSCILLATOR DAC STEREO PDM MODULATOR DAC BIDIRECTIONAL ASRCS SERIAL INPUT/ OUTPUT PORT I2C/SPI CONTROL INTERFACE AND SELF-BOOT ADC_SDATA1/CLKOUT/MP6 XTALI/MCLKIN XTALO HPOUTLP/LOUTLP HPOUTLN/LOUTLN HPOUTRP/LOUTRP HPOUTRN/LOUTRN DAC_SDATA/MP0 ADC_SDATA0/PDMOUT/MP1 BCLK/MP2 LRCLK/MP3 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADAU1772 Data Sheet SPECIFICATIONS Master clock = core clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. PLL disabled, direct master clock. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Single-Ended Line Input PGA Inputs SINGLE-ENDED LINE INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR)2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio SINGLE-ENDED PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Test Conditions/Comments All ADCs Min Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 0 dB gain −12 dB gain 0 dB gain +35.25 dB gain PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dBFS AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 22 μF CM capacitor = 22 μF 100 mV p-p at 1 kHz PGA_ENx = 1, PGA_x_BOOST = 0 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Typ 24 0.375 95 Max Unit Bits dB dB 14.3 32.0 20 0.68 AVDD/3.63 0.49 1.38 0.90 2.54 97 102 94 99 98 103 96 100 40 −90 −94 ±0.1 ±0.2 100 55 AVDD/3.63 0.49 1.38 0.90 2.54 96 102 94 99 kΩ kΩ kΩ kΩ V rms V rms V p-p V rms V p-p dB dB dB dB dB dB dB dB mdB dB dB mV dB dB dB V rms V rms V p-p V rms V p-p dB dB dB dB Rev. C \| Page 4 of 116 5 Page ADAU1772 Data Sheet DIGITAL TIMING SPECIFICATIONS −40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V. Table 7. Digital Timing Parameter MASTER CLOCK tMP tMCLK SERIAL PORT tBL tBH tLS tLH tSS tSH tTS tSOD tSOTD tSOTX SPI PORT fSCLK tCCPL tCCPH tCLS tCLH tCLPH tCDS tCDH tCOD I2C PORT fSCL tSCLH tSCLL tSCS tSCR tSCH tDS tSCF tSDF tBFT I2C EEPROM SELF-BOOT tSCHE tSCSE tBFTE tDSE tBHTE MULTIPURPOSE AND POWER- DOWN PINS tGIL tRLPW TMIN Limit TMAX 37 125 77 82 40 40 10 10 5 5 10 0 34 30 30 6.25 80 80 5 100 80 10 10 101 400 0.6 1.3 0.6 250 0.6 100 250 250 0.6 26 × tMP – 70 38 × tMP – 70 70 × tMP – 70 6 × tMP – 70 32 × tMP 1.5 × 1/fS 20 Unit Description ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL ns Internal MCLK period; direct MCLK and PLL output divided by 2 ns BCLK low pulse width (master and slave modes) ns BCLK high pulse width (master and slave modes) ns LRCLK setup; time to BCLK rising (slave mode) ns LRCLK hold; time from BCLK rising (slave mode) ns DAC_SDATA setup; time to BCLK rising (master and slave modes) ns DAC_SDATA hold; time from BCLK rising (master and slave modes) ns BCLK falling to LRCLK timing skew (master mode) ns ADC_SDATAx delay; time from BCLK falling (master and slave modes) ns BCLK falling to ADC_SDATAx driven in TDM tristate mode ns BCLK falling to ADC_SDATAx tristated in TDM tristate mode MHz SCLK frequency ns SCLK pulse width low ns SCLK pulse width high ns SS setup; time to SCLK rising ns SS hold; time from SCLK rising ns SS pulse width high ns MOSI setup; time to SCLK rising ns MOSI hold; time from SCLK rising ns MISO delay; time from SCLK falling kHz SCL frequency µs SCL high µs SCL low µs SCL rise setup time (to SDA falling), relevant for repeated start condition ns SCL and SDA rise time, CLOAD = 400 pF µs SCL fall hold time (from SDA falling), relevant for start condition ns SDA setup time (to SCL rising) ns SCL fall time; CLOAD = 400 pF ns SDA fall time; CLOAD = 400 pF µs SCL rise setup time (to SDA rising), relevant for stop condition ns SCL fall hold time (from SDA falling), relevant for start condition; tMP is the input clock on the MCLKIN pin ns SCL rise setup time (to SDA falling), relevant for repeated start condition ns SCL rise setup time (to SDA rising), relevant for stop condition ns Delay from SCL falling to SDA changing ns SDA rising in self-boot stop condition to SDA falling edge for external master start condition µs MPx input latency; time until high or low value is read by core ns PD low pulse width Rev. C \| Page 10 of 116 11 Page

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