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PDF ADE9078 Data sheet ( Hoja de datos )
| Número de pieza | ADE9078 | |
| Descripción | Polyphase Energy Metering AFE | |
| Fabricantes | Analog Devices | |
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Data Sheet
High Performance, Polyphase
Energy Metering AFE
ADE9078
FEATURES
FUNCTIONAL BLOCK DIAGRAM
7 high performance analog-to-digital converters (ADCs)
101 dB signal-to-noise ratio (SNR)
10,000:1 dynamic range
Wide input range: ±1 V, 0.707 V rms full scale
Differential inputs
±25 ppm/°C maximum channel temperature drift (including
ADC, internal VREF, and PGA drift) enabling Class 0.2
meters with standard external components
Power quality measurements
Line frequency: 1 measurement per phase
Zero crossing detection, zero-crossing timeout
Phase angle measurements
Supports current transformers (CTs) and Rogowski coil
(di/dt) sensors
Multiple range phase/gain compensation for CTs
Digital integrator for Rogowski coils
Flexible waveform buffer
Able to resample waveform to ensure 64 points per line
cycle for ease of external harmonic analysis
Events can trigger waveform storage
Simplifies data collection for IEC 61000-4-7 harmonic analysis
Advanced metrology feature set
Total active power, volt-amperes reactive (VAR), volt-
amperes (VA), watthour, VAR-hour, and VA-hour
Fundamental VAR and VAR-hour
Current and voltage rms per phase (xIRMS, xVRMS)
Supports active energy standards: IEC 62053-21,
IEC 62053-22; EN50470-3; OIML R46, ANSI C12.20
Supports reactive energy standards: IEC 62053-23,
IEC 62053-4
High speed communication port
10 MHz serial peripheral interface (SPI)
APPLICATIONS
Polyphase meters
Power quality monitoring
Protective device
GENERAL DESCRIPTION
The ADE90781 is a highly accurate, fully integrated energy
metering device. Interfacing with both current transformer
(CT) and Rogowski coil sensors, the ADE9078 enables users to
develop a 3-phase metrology platform, which achieves high
performance for Class 1 up to Class 0.2 meters.
LDO ADE9078
PGA
ADC
METROLOGY FEATURES
PGA
ADC
PGA
ADC
SINC4
AND
PGA
ADC
DECIMATION
PGA
ADC
(PER PHASE)
IRMS, VRMS
ACTIVE POWER, VA
WATTHOUR, VA-Hr
WAVEFORM BUFFER
LINE FREQUENCY
ETC.
PGA
ADC
PGA
ADC
1.25V
REFERENCE
Figure 1.
CF1
TO CF4
IRQ0
IRQ1
SPI
The ADE9078 integrates seven high performances ADCs and a
flexible DSP core. An integrated high end reference ensures low
drift over temperature with a combined drift of less than
±25 ppm/°C maximum per channel, each of which includes a
programmable gain amplifier (PGA) and ADC.
The ADE9078 offers an integrated flexible waveform buffer that
stores samples at a fixed data rate or a sampling rate that varies
based on line frequency to ensure 64 points per line cycle. These
two options make it easy to implement harmonic analysis in an
external processor according to IEC 61000-4-7.
Two power modes are provided to enable detection of meter
tampering: PSM2 uses a low power comparator to compare
current channels to a threshold and indicates whether it is
exceeded on the IRQ0 and IRQ1 outputs; PSM1 enables fast
measurement of current and voltage rms (xVRMS and xIRMS),
active power, and VAR during a tamper.
The ADE9078 allows advanced and highly accurate energy
measurements, enabling one platform to cover a wide range of
meters, through a combination of various high end metrology
features and superior analog performance.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. Other patents are pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADE9078
Data Sheet
SPECIFICATIONS
VDD = 2.7 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 12.288 MHz crystal (XTAL), TMIN to TMAX = −40°C to
+85°C for minimum and maximum specifications, TA = 25°C (typical) for typical specifications.
Table 1.1
Parameter
ACCURACY
Total Active Energy
Total Reactive Energy
Total Apparent Energy
Fundamental Reactive
IRMS, VRMS
Active Power, VAR
Power Factor (PF)
64-Point per Line Cycle
Resampled Data
Min
Line Period Measurement
Current to Current, Voltage to
Voltage, and Voltage to
Current Angle Measurement
PSM1 IRMS
Typ
0.1
0.2
0.1
0.2
0.1
0.5
0.1
0.2
0.1
0.5
0.2
±0.001
0.1
Max
0.3
−72
3
−38
0.001
0.036
0.2
Rev. 0 | Page 4 of 107
Unit
%
%
%
%
%
%
%
%
%
%
%
%
%
dB
%
dB
Hz
Degrees
Test Conditions/Comments
Measurement error per phase
Over a dynamic range of 5000 to 1, 10 sec
accumulation; gain compensation only
Over a dynamic range of 10,000 to 1, 20 sec
accumulation; gain compensation only
Over a dynamic range of 5000 to 1, 10 sec
accumulation; gain compensation only
Over a dynamic range of 10,000 to 1, 20 sec
accumulation; gain compensation only
Over a dynamic range of 1000 to 1, 2 sec
accumulation
Over a dynamic range of 5000 to 1, 10 sec
accumulation
Over a dynamic range of 5000 to 1, 2 sec
accumulation
Over a dynamic range of 10,000 to 1,
20 sec accumulation
Over a dynamic range of 1000 to 1
Over a dynamic range of 5000 to 1
Over a dynamic range of 5000 to 1, 1 sec
accumulation
Over a dynamic range of 5000 to 1
An FFT is performed to receive the magni-
tude response; this error is the worst case
error in the fundamental magnitude caused
by resampling algorithm distortion; input
signal is 50 Hz fundamental on voltage
channel and fundamental with ninth har-
monic at half of full scale on current channel
An FFT is performed to receive the magni-
tude response; this error is the magnitude
error of ninth harmonic caused by the
resampling algorithm distortion input signal
is 50 Hz fundamental with ninth harmonic
at half of full scale on current channel
Amplitude of highest spur; input signal is
50 Hz fundamental and ninth harmonic
at half of full scale on the current channel
An FFT is performed to receive the magni-
tude response; this error is the magnitude
error of 31st harmonic caused by resampling
algorithm distortion; input signal is 50 Hz
fundamental with 31st harmonic at half of
full scale on the current channel
Amplitude of highest spur; input signal is
50 Hz fundamental and 31st harmonic at
half of full scale on the current channel
Resolution at 50 Hz
Resolution at 50 Hz; voltage and current
at 1/10th of full scale
% Accuracy achieved 40 ms after entering
PSM1 mode at 600:1
5 Page 
ADE9078
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
PULL_HIGH 1
DGND 2
DVDDOUT 3
PM0 4
PM1 5
RESET 6
IAP 7
IAN 8
IBP 9
IBN 10
ADE9078
TOP VIEW
(Not to Scale)
30 CLKOUT
29 CLKIN
28 GND
27 VDD
26 AGND
25 AVDDOUT
24 VCP
23 VCN
22 VBP
21 VBN
NOTES
1. IT IS RECOMMENDED TO TIE THE
NC1 AND NC2 PINS TO GROUND.
2. EXPOSED PAD. CREATE A SIMILAR PAD ON THE
PRINTED CIRCUIT BOARD (PCB) UNDER THE
EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE
PAD ON THE PCB TO CONFER MECHANICAL STRENGTH
TO THE PACKAGE AND CONNECT ALL GROUNDS
(GND, AGND, DGND, AND REFGND) TOGETHER AT
THIS POINT.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Description
1 PULL_HIGH
2 DGND
Pull High. Tie this pin to VDD.
Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9078. Because
the digital return currents in the ADE9078 are small, it is acceptable to connect this pin to the analog
ground plane of the whole system. Connect all grounds (GND, AGND, DGND, and REFGND) together at one
point.
3 DVDDOUT
1.8 V Output of the Digital Low Dropout Regulator (LDO). Decouple this pin with a 0.1 μF ceramic
capacitor in parallel with a ceramic 4.7 μF capacitor.
4 PM0
Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, PM0 and
PM1 must be grounded (see the Power Modes section).
5 PM1
Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, PM0 and
PM1 must be grounded (see the Power Modes section).
6 RESET
Reset Input, Active Low. This pin must stay low for at least 1 μs to trigger a hardware reset.
7, 8 IAP, IAN
Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
9, 10 IBP, IBN
Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
11, 12 ICP, ICN
Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
13, 14 INP, INN
Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage
inputs with a maximum differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
15 REFGND
Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND)
together at one point.
16 REF
Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference
has a nominal value of 1.25 V. An external reference of 1.2 V to 1.25 V can also be connected at this pin. In
either case, decouple REF to REFGND with 0.1 μF ceramic capacitor in parallel with a ceramic 4.7 μF capacitor.
After reset, the on-chip reference is enabled. To use the internal voltage reference with external circuits, a
buffer is required. The full-scale values mentioned in this data sheet are for a voltage reference of 1.25 V.
17 NC1
No Connection. It is recommended to tie this pin to ground.
18 NC2
No Connection. It is recommended to tie this pin to ground.
Rev. 0 | Page 10 of 107
11 Page | ||
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| PDF Descargar | [ Datasheet ADE9078.PDF ] | |
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