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PDF AD6657A Data sheet ( Hoja de datos )
| Número de pieza | AD6657A | |
| Descripción | Quad IF Receiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Quad IF Receiver
AD6657A
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD DRGND
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
VIN+C
VIN–C
VCMC
VIN+D
VIN–D
VCMD
AD6657A
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
14
PIPELINE
NOISE SHAPING 11
ADC
REQUANTIZER
14 11
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
14
PIPELINE
NOISE SHAPING 11
ADC
REQUANTIZER
DCO±AB
DO±AB
PORT A
D10±AB
DCO±CD
DO±CD
PORT B
D10±CD
REFERENCE
SERIAL PORT
CLOCK
DIVIDER
MODE
SYNC
PDWN
SCLK SDIO CSB
Figure 1.
CLK+ CLK–
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657A supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth while
maintaining an 11-bit output resolution. The NSR block can be
programmed to provide a bandwidth of either 22%, 33%, or 36% of
the sample clock. For example, with a sample clock rate of
185 MSPS, the AD6657A can achieve up to 76.0 dBFS SNR for a
40 MHz bandwidth in the 22% mode, up to 73.6 dBFS SNR for a
60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS SNR for a
65 MHz bandwidth in the 36% mode.
(General Description continued on Page 3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD6657A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUT
Input Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance2
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
Sine Wave Input1
Standby Power3
Power-Down Power
Temperature Min
Full 11
Full
Full −0.9
Full +4
Full −0.4
Full −0.55
Full −5
Full 0
Full
Full
Full 1.4
Full
Full
Full
Full 1.7
Full 1.7
Full
Full
Full
Full
Full
Typ Max
Guaranteed
+0.1
+11
±0.1
±0.17
+0.9
+18
+0.4
+0.55
+3 +11
+2.1 +8
2
40
1.75 2.0
0.95
20
5
1.8
1.8
466
170
1145
129
3.8
1.9
1.9
510
183
1247
10
Unit
Bits
mV
% FSR
LSB
LSB
mV
% FSR
ppm/°C
ppm/°C
V p-p
V
kΩ
pF
V
V
mA
mA
mW
mW
mW
1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. A | Page 4 of 36
5 Page 
AD6657A
Data Sheet
TIMING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 5.
Parameter
Description
Min Typ Max Unit
SYNC TIMING REQUIREMENTS See Figure 3 for details
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
See Figure 60 for details, except where noted
0.24 ns
0.40 ns
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge (not pictured in
Figure 60)
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge (not pictured in
Figure 60)
10
ns
Sync Input Timing Diagram
CLK+
SYNC
tSSYNC
tHSYNC
Figure 3. SYNC Input Timing Requirements
Rev. A | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6657A.PDF ] | |
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