|
|
PDF AD7405 Data sheet ( Hoja de datos )
| Número de pieza | AD7405 | |
| Descripción | 16-Bit Isolated Sigma-Delta Modulator / LVDS Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7405 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
Data Sheet
16-Bit, Isolated Sigma-Delta Modulator,
LVDS Interface
AD7405
FEATURES
5 MHz to 20 MHz external clock input rate
16 bits, no missing codes
Signal-to-noise ratio (SNR): 88 dB typical
Effective number of bits (ENOB): 14.2 bits typical
Typical offset drift vs. temperature: 1.6 µV/°C
Low voltage differential signaling (LVDS) interface
On-board digital isolator
On-board reference
Full-scale analog input voltage range: ±320 mV
−40°C to + 125°C operating temperature range
High common-mode transient immunity: >25 kV/µs
16-lead, wide-body SOIC_IC, with increased creepage
package
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Maximum working insulation voltage (VIORM): 1250 VPEAK
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Data acquisition systems
Analog-to-digital and opto-isolator replacements
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
AD7405
BUF
VIN+
VIN–
REF
Σ-Δ ADC
CLK
DECODER
DATA
ENCODER
CLK
ENCODER
DATA
DECODER
MCLKIN+
(5MHz TO
20MHz)
MCLKIN–
MDAT+
MDAT–
GND1
Figure 1.
GND2
GENERAL DESCRIPTION
The AD74051 is a high performance, second-order, Σ-Δ modulator
that converts an analog input signal into a high speed, single-bit
LVDS data stream, with on-chip digital isolation based on
Analog Devices, Inc., iCoupler® technology. The AD7405 operates
from a 4.5 V to 5.5 V (VDD1) power supply and accepts a
differential input signal of ±250 mV (±320 mV full-scale). The
differential input is ideally suited to shunt voltage monitoring in
high voltage applications where galvanic isolation is required.
The analog input is continuously sampled by a high performance
analog modulator, and converted to a ones density digital output
stream with a data rate of up to 20 MHz. The original information
can be reconstructed with an appropriate digital filter to achieve
88 dB SNR at 78.1 kSPS. The LVDS input/output can use a 3 V
to 5.5 V supply (VDD2).
The LVDS interface is digitally isolated. The LVDS interface
technology, combined with monolithic transformer technology,
means the on-chip isolation provides outstanding performance
characteristics, superior to alternatives such as optocoupler
devices. The AD7405 device is offered in a 16-lead, wide-body
SOIC_IC package and has an operating temperature range of
−40°C to +125°C.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7405
Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +125°C, unless otherwise noted. Sample tested during initial release to ensure
compliance. It is recommended to read the MDAT signal on the MCLKIN+ rising edge.
Table 2.
Parameter1
fMCLKIN
t1
t2
t3
t4
Limit at TMIN, TMAX
5
20
30
40
10
10
0.45 × tMCLKIN
0.48 × tMCLKIN
0.45 × tMCLKIN
0.48 × tMCLKIN
Unit
MHz minimum
MHz maximum
ns maximum
ns maximum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
ns minimum
Description
Master clock input frequency
Data access time after MCLKIN+ rising edge
VDD2 = 4.5 V to 5.5 V
VDD2 = 3 V to 3.6 V
Data hold time after MCLKIN+ rising edge
VDD2 = 4.5 V to 5.5 V
VDD2 = 3 V to 3.6V
Master clock low time
fMCLKIN ≤ 16 MHz
16 MHz < fMCLKIN ≤ 20 MHz
Master clock high time
fMCLKIN ≤ 16 MHz
16 MHz < fMCLKIN ≤ 20 MHz
1 Sample tested during initial release to ensure compliance.
MCLKIN–
MCLKIN+
MDAT–
MDAT+
t4
t1 t2
t3
Figure 2. Data Timing
Rev. A | Page 4 of 20
5 Page 
AD7405
800
692381
MCLKIN = 10MHz
700 VIN+ = VIN– = 0V
1M SAMPLES
600
500
400
300
200
144470
160941
100
0 1147
1061
0
0
32764 32765 32766 32767 32768 32769 32770
CODE
Figure 11. Histogram of Codes at Code Center
100
fIN = 1kHz
90
SNR
SINAD
80
70
60
–50
–25 0
25 50 75 100 125
TEMPERATURE (°C)
Figure 12. SNR and SINAD vs. Temperature
150
–60
fIN = 1kHz
–70
–80
–90
–100
THD
SFDR
–110
–120
–50
–25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 13. THD and SFDR vs. Temperature
150
Data Sheet
200
MCLKIN = 20MHz
150
100
50
0
–50
–100
–150
–200
–50
–25
0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 14. Offset vs. Temperature
10
8
6
4
2
0
–2
–4
–6
–8
–10
–50
MCLKIN = 10MHz
MCLKIN = 20MHz
–25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 15. Gain Error vs. Temperature
150
35
30
25
20
15 MCLKIN = 20MHz, –40°C
MCLKIN = 20MHz, +25°C
MCLKIN = 20MHz, +85°C
10 MCLKIN = 20MHz, +125°C
MCLKIN = 10MHz, –40°C
MCLKIN = 10MHz, +25°C
5 MCLKIN = 10MHz, +85°C
MCLKIN = 10MHz, +125°C
0
4.50 4.75 5.00 5.25 5.50
VDD1 (V)
Figure 16. IDD1 vs. VDD1 at Various Temperatures and Clock Rates
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7405.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7400 | Isolated Sigma-Delta Modulator | Analog Devices |
| AD7400A | Isolated Sigma-Delta Modulator | Analog Devices |
| AD7401 | Isolated Sigma-Delta Modulator | Analog Devices |
| AD7401A | Isolated Sigma-Delta Modulator | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |