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PDF AD7779 Data sheet ( Hoja de datos )
| Número de pieza | AD7779 | |
| Descripción | Simultaneous Sampling ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
FEATURES
8-channel, 24-bit simultaneous sampling analog-to-digital
converter (ADC)
Single-ended or true differential inputs
Programmable gain amplifier (PGA) per channel (gains of
1, 2, 4, and 8)
Low dc input current: ±4 nA
Up to 16 kSPS output data rate (ODR) per channel
Programmable ODRs and bandwidth
Sample rate converter (SRC) for coherent sampling
Sampling rate resolution up to 15.2 µSPS
Low latency sinc3 filter path
Adjustable phase synchronization
Internal 2.5 V reference
Two power modes
High resolution mode
Low power mode
Optimizes power dissipation and performance
Low resolution successive approximation (SAR) ADC for
system and chip diagnostics
Power supply
Bipolar (±1.65 V) or unipolar (3.3 V) supplies
Digital input/output (I/O) supply: 1.8 V to 3.6 V
Performance temperature range: –40°C to +105°C
Functional temperature range: –40°C to +125°C
Performance
Combined ac and dc performance
108 dB signal-to-noise ratio (SNR)/dynamic range at 16 kSPS
in high resolution mode
−109 dB total harmonic distortion (THD)
±7 ppm integral nonlinearity (INL)
±40 µV offset error
±0.1% gain error
±10 ppm/°C typical temperature coefficient
APPLICATIONS
Circuit breakers
General-purpose data acquisition
Electroencephalography (EEG)
Industrial process control
GENERAL DESCRIPTION
The AD7779 is an 8-channel, simultaneous sampling ADC.
There are eight full Σ-Δ ADCs on chip. The AD7779 provides
an ultralow input current to allow direct sensor connection. Each
input channel has a programmable gain stage allowing gains of
1, 2, 4, and 8 to map lower amplitude sensor outputs into the
full-scale ADC input range, maximizing the dynamic range of
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
8-Channel, 24-Bit,
Simultaneous Sampling ADC
AD7779
the signal chain. The AD7779 accepts VREF from 1 V up to 3.6 V.
The analog inputs accept unipolar (0 V to VREF/GAIN) or true
bipolar (±VREF/GAIN/2 V) analog input signals with 3.3 V or
±1.65 V analog supply voltages. The analog inputs can be
configured to accept true differential, pseudo differential, or single-
ended signals to match different sensor output configurations.
Each channel contains an ADC modulator and a sinc3, low
latency digital filter. An SRC is provided to allow fine resolution
control over the AD7779 ODR. This control can be used in
applications where the ODR resolution is required to maintain
coherency with 0.01 Hz changes in the line frequency. The SRC
is programmable through the serial port interface (SPI). The
AD7779 implements two different interfaces: a data output
interface and SPI control interface. The ADC data output
interface is dedicated to transmitting the ADC conversion
results from the AD7779 to the processor. The SPI interface
is used to write to and read from the AD7779 configuration
registers and for the control and reading of data from the SAR
ADC. The SPI interface can also be configured to output the
Σ-Δ conversion data.
The AD7779 includes a 12-bit SAR ADC. This ADC can be used
for AD7779 diagnostics without having to decommission one of
the Σ-Δ ADC channels dedicated to system measurement func-
tions. With the use of an external multiplexer, which can be
controlled through the three general-purpose inputs/outputs pins
(GPIOs), and signal conditioning, the SAR ADC can be used to
validate the Σ-Δ ADC measurements in applications where
functional safety is required. In addition, the AD7779 SAR ADC
includes an internal multiplexer to sense internal nodes.
The AD7779 contains a 2.5 V reference and reference buffer.
The reference has a typical temperature coefficient of 10 ppm/°C.
The AD7779 offers two modes of operation: high resolution
mode and low power mode. High resolution mode provides a
higher dynamic range while consuming 10.75 mW per channel;
low power mode consumes just 3.37 mW per channel at a
reduced dynamic range specification.
The specified operating temperature range is −40°C to +105°C,
although the device is operational up to +125°C.
Note that throughout this data sheet, certain terms are used to
refer to either the multifunction pins or a range of pins. The
multifunction pins, such as DCLK0/SDO, are referred to either
by the entire pin name or by a single function of the pin, for
example, DCLK0, when only that function is relevant. In the
case of ranges of pins, AVSSx refers to the following pins:
AVSS1A, AVSS1B, AVSS2A, AVSS2B, AVSS3, and AVSS4.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7779
REVISION HISTORY
9/2016—Rev. 0 to Rev. A
Changes to General Description Section ...................................... 1
Changes to Table 1............................................................................ 6
Changes to Table 2.......................................................................... 10
Changes to Table 4.......................................................................... 12
Changes to Figure 8 Caption through Figure 13 Caption......... 18
Changes to Figure 14 Caption and Figure 17 Caption .............. 19
Changes to Figure 22...................................................................... 20
Changes to Figure 26 Caption, Figure 27 Caption, Figure 29
Caption, and Figure 30 Caption ................................................... 21
Changes to Figure 35 Caption....................................................... 22
Changes to Figure 38 through Figure 43 ..................................... 23
Changes to Figure 44, Figure 45 Caption, and Figure 47 .......... 24
Changes to Figure 51 Caption, Figure 52 Caption, and
Figure 55 Caption ........................................................................... 25
Changes to Figure 56, Figure 58, Figure 59, and Figure 61....... 26
Changes to Figure 63 Caption, Figure 64 Caption, Figure 66
Caption, and Figure 67 Caption ................................................... 27
Changes to Figure 76 and Figure 79............................................. 29
Changes to Figure 80 and Figure 81............................................. 30
Changes to Figure 100.................................................................... 44
Changes to SPI SAR Diagnostic Mode (SPI Control Mode)
Section.............................................................................................. 46
Changes to SPI Transmission Errors (SPI Control Mode) ....... 48
Changes to CRC Header Section, Figure 107, and Table 33 to
Table 35 ............................................................................................ 51
Changes to SRC Bandwidth Section ............................................ 52
Changes to Figure 109, Figure 110, SRC Group Delay and
Latency Section, and Setting Time Section................................. 53
Added Figure 111 and Figure 112; Renumbered Sequentially.....53
Changes to Table 40..............................................................................57
Changes to Calculating the CRC Checksum Section and
Table 42 ............................................................................................ 58
Changes to SPI Control Mode Checksum Section .................... 59
Changes to Table 66........................................................................ 74
2/2016—Revision 0: Initial Version
Data Sheet
Rev. A | Page 4 of 100
5 Page 
AD7779
Data Sheet
DOUTx TIMING CHARACTERISTISTICS
AVDD1x/AVSSx = ±1.65 V, 3.3 V/AGND, AVDD2 − AVSSx = 2.2 V to 3.6 V; IOVDD = 1.8 V to 3.6 V; DGND = 0 V, REFx+/REFx− =
2.5 V (internal/external), MCLK = 8192 kHz; all specifications at TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Description1
MCLK frequency
MCLK low time
MCLK high time
DCLKx high time
DCLKx low time
MCLK falling edge to DCLK rising edge
MCLK falling edge to DCLK falling edge
DCLKx rising edge to DRDY rising edge
DCLKx rising edge to DRDY falling edge
DOUTx setup time
DOUTx hold time
Test Conditions/Comments
50:50
MCLK/2
MCLK/2
Min
0.655
60
60
121
121
2
1
20
20
Typ Max
8.192
45
45
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH)/2.
MCLK
DCLK
DRDY
DOUTx
t2
t3
t1
t4 t5
t8
t9
t6
t7
LSB
MSB
MSB – 1
t10 t11
LSB + 1
LSB
Figure 2. Data Interface Timing Diagram
Rev. A | Page 10 of 100
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7779.PDF ] | |
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