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부품번호 AD7768-4 기능
기능 Simultaneous Sampling ADC
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AD7768-4 데이터시트, 핀배열, 회로
Data Sheet
8-/4-Channel, 24-Bit, Simultaneous Sampling
ADCs with Power Scaling, 110.8 kHz BW
AD7768/AD7768-4
FEATURES
Precision ac and dc performance
8-/4-channel simultaneous sampling
256 kSPS maximum ADC output data rate per channel
108 dB dynamic range
110.8 kHz maximum input bandwidth (−3 dB bandwidth)
−120 dB total harmonic distortion (THD) typical
±2 ppm of full-scale range (FSR) integral nonlinearity
(INL), ±50 µV offset error, ±30 ppm gain error
Optimized power dissipation vs. noise vs. input bandwidth
Selectable power, speed, and input bandwidth (BW) modes
Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel
Median: half speed, 55.4 kHz BW, 27.5 mW per channel
Eco: lowest power, 13.8 kHz BW, 9.375 mW per channel
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
Cyclic redundancy check (CRC) error checking on data interface
Daisy-chaining
Linear phase digital filter
Low latency sinc5 filter
Wideband brick wall filter: ±0.005 dB pass-band ripple
from dc to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5.0 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
Temperature range: −40°C to +105°C
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio test and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
FUNCTIONAL BLOCK DIAGRAM
AVDD1A,
AVDD1B REFx+ REFx–
AVDD2A, REGCAPA,
AVDD2B REGCAPB DGND IOVDD DREGCAP
BUFFERED
VCM
VCM
VCM
PRECHARGE
×8 REFERENCE
BUFFERS
1.8V
LDO
AIN0+
CH 0
AIN0–
AIN1+
CH 1
AIN1–
AIN2+
CH 2
AIN2–
AIN3+
CH 3
AIN3–
AIN4+
CH 4*
AIN4–
AIN5+
CH 5*
AIN5–
AIN6+
CH 6*
AIN6–
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
Σ-Δ
ADC
DIGITAL
FILTER
ENGINE
SINC5
LOW LATENCY
FILTER
WIDEBAND
LOW RIPPLE
FILTER
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
OFFSET,
GAIN PHASE
CORRECTION
1.8V
LDO
ADC
OUTPUT
DATA
SERIAL
INTERFACE
SPI
CONTROL
INTERFACE
SYNC_IN
SYNC_OUT
START
RESET
FORMAT1*
FORMAT0
DRDY
DCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4*
DOUT5*
DOUT6*, DIN
DOUT7*
ST0/CS
ST1*/SCLK
DEC0/SDO
DEC1/SDI
AIN7+
CH 7*
AIN7–
P
Σ-Δ
P ADC
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
OFFSET,
GAIN PHASE
CORRECTION
AD7768/AD7768-4
PIN/SPI
AVSS
XTAL2/MCLK
*THESE CHANNELS/PINS EXIST ONLY ON THE AD7768.
Figure 1.
XTAL1
MODE3/GPIO3 FILTER/GPIO4
TO
MODE0/GPIO0
Rev. A
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




AD7768-4 pdf, 반도체, 판매, 대치품
AD7768/AD7768-4
Added Table 64 and Table 65.................................................................88
Added Table 66, Table 67, and Table 68...............................................89
Added Table 69.........................................................................................90
Added Table 70 and Table 71.................................................................91
Added Table 72 and Table 73.................................................................92
Added Table 74 and Table 75.................................................................93
Added Table 76, Table 77, and Table 78...............................................94
Data Sheet
Added Table 79, Table 80, and Table 81...............................................95
Added Table 82, Table 83, Table 84, and Table 85..............................96
Added Table 86 and Table 87.................................................................97
Added Table 88.........................................................................................98
Changes to Ordering Guide...................................................................99
1/16—Revision 0: Initial Version
Rev. A | Page 4 of 99

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AD7768-4 전자부품, 판매, 대치품
Data Sheet
AD7768/AD7768-4
Parameter
ACCURACY
INL
Offset Error4
Offset Error Drift
Gain Error4
Gain Drift vs. Temperature2
VCM PIN
Output
Load Regulation (∆VOUT/∆IL)
Voltage Regulation
Short-Circuit Current
ANALOG INPUTS
Differential Input Voltage Range
Input Common-Mode Range2
Absolute Analog Input
Voltage Limits2
Analog Input Current
Unbuffered
Precharge Buffer On5
Input Current Drift
Unbuffered
Precharge Buffer On
EXTERNAL REFERENCE
Reference Voltage
Absolute Reference Voltage
Limits2
Average Reference Current
Average Reference Current Drift
Common-Mode Rejection
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter
Decimation Rate
Group Delay
Settling Time
Pass-Band Ripple2
Pass Band
Stop Band Frequency
Stop Band Attenuation
Test Conditions/Comments
See Table 2 for 1.8 V operation
Endpoint method
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency2
DCLK frequency ≤ 24 MHz
24 MHz to 32.768 MHz DCLK frequency
TA = 25°C
With respect to AVSS
Applies to the following VCM output
options only: VCM = ∆VOUT/∆(AVDD1 −
AVSS)/2; VCM = 1.65 V; and VCM = 2.5 V
See the Analog Inputs section
VREF = (REFx+) − (REFx−)
Fast mode
Differential component
Common-mode component
Fast mode; see Figure 62
VREF = (REFx+) − (REFx−)
Reference precharge buffers off
Reference precharge buffer on
Fast mode; see Figure 63
Reference precharge buffers off
Reference precharge buffers on
Fast mode; see Figure 63
Reference precharge buffers off
Reference precharge buffers on
FILTER = 0
Up to six selectable decimation rates; see
the Decimation Rate Control section
Latency
Complete settling, see Table 35
From dc to 102.4 kHz at 256 kSPS
±0.005 dB bandwidth
−0.1 dB bandwidth
−3 dB bandwidth
Attenuation > 105 dB
See the Wideband Low Ripple Filter section
Min
−VREF
AVSS
AVSS
1
AVSS − 0.05
AVSS
32
Typ
±2
±50
±75
±250
±750
±30
±0.5
(AVDD1 −
AVSS)/2
400
5
30
±48
±17
−20
±5
±31
±72
±16
±1.7
±49
95
34/ODR
68/ODR
0.4 × ODR
0.409 × ODR
0.433 × ODR
0.499 × ODR
105
Max
±7
±115
±150
±70
±1
+VREF
AVDD1
AVDD1
AVDD1 − AVSS
AVDD1 + 0.05
AVDD1
1024
±0.005
Unit
ppm of FSR
µV
µV
nV/°C
nV/°C
ppm of FSR
ppm/°C
V
µV/mA
µV/V
mA
V
V
V
µA/V
µA/V
µA
nA/V/°C
nA/°C
V
V
V
µA/V/channel
µA/V/channel
nA/V/°C
nA/V/°C
dB
sec
sec
dB
Hz
Hz
Hz
Hz
dB
Rev. A | Page 7 of 99

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AD7768-4

Simultaneous Sampling ADC

Analog Devices
Analog Devices

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