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AD7622 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD7622은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 AD7622 기능
기능 2 MSPS PulSAR ADC
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AD7622 데이터시트, 핀배열, 회로
16-Bit, 1.5 LSB INL, 2 MSPS PulSAR® ADC
AD7622
FEATURES
Throughput
2 MSPS (wideband warp and warp mode)
1.5 MSPS (normal mode)
INL: ±0.5 LSB typical, ±1.5 LSB maximum (±23 ppm of FSR)
16-bit resolution with no missing codes
Dynamic range: 92.5 dB typical
SINAD: 91 dB minimum @ 20 kHz (VREF = 2.5 V)
THD: −115 dB typical @ 20 kHz (VREF = 2.5 V)
2.048 V internal reference: typical drift 8 ppm/°C; TEMP output
Differential input range: ±VREF (VREF up to 2.5 V)
No pipeline delay (SAR architecture)
Parallel (16-, or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
Single 2.5 V supply operation
Power dissipation
70 mW typical @ 2 MSPS with internal REF
2 μW in power-down mode
Pb-free, 48-lead LQFP and 48-lead LFCSP_VQ
Pin compatible with other PulSAR 48-lead ADCs
APPLICATIONS
Medical instruments
High speed data acquisition/high dynamic data acquisition
Digital signal processing
Spectrum analysis
Instrumentation
Communications
ATE
GENERAL DESCRIPTION
The AD7622 is a 16-bit, 2 MSPS, charge redistribution SAR,
fully differential, analog-to-digital converter (ADC) that
operates from a single 2.5 V power supply. The part contains a
high speed, 16-bit sampling ADC, an internal conversion clock,
an internal reference (and buffer), error correction circuits, and
both serial and parallel system interface ports. It features two
very high sampling rate modes (wideband warp and warp) and
a fast mode (normal) for asynchronous rate applications. The
AD7622 is hardware factory calibrated and tested to ensure ac
parameters, such as signal-to-noise ratio (SNR), in addition to
the more traditional dc parameters of gain, offset, and linearity.
The AD7622 is available in Pb-free only packages with
operation specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
TEMP REFBUFIN REF REFGND
DVDD DGND
AGND
AVDD
IN+
IN–
PDREF
PDBUF
PD
RESET
REF
REF AMP
SWITCHED
CAP DAC
AD7622
SERIAL
PORT 16
PARALLEL
INTERFACE
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
OVDD
OGND
D[15:0]
SER/PAR
BUSY
RD
CS
OB/2C
BYTESWAP
WARP NORMAL CNVST
Figure 1.
Table 1. PulSAR 48-Lead ADC Selection
Type/kSPS
100 to
250
500 to
570
650 to
1000
Pseudo
Differential
AD7651,
AD7660,
AD7661
AD7650,
AD7652,
AD7664,
AD7666
AD7653,
AD7667
True Bipolar
AD7610, AD7665 AD7612,
AD7663
AD7671
True
Differential
AD7675 AD7676 AD7677
18-Bit
Multichannel/
Simultaneous
AD7631,
AD7678
AD7679
AD7654
AD7634,
AD7674
AD7655
>1000
AD7621,
AD7622,
AD7623
AD7641,
AD7643
1.50
POSITIVE INL = +0.43 LSB
NEGATIVE INL = –0.49 LSB
1.00
0.50
0
–0.50
–1.00
–1.50
0
16384
32768
CODE
49152
Figure 2. Integral Nonlinearity vs. Code
65536
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.




AD7622 pdf, 반도체, 판매, 대치품
SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance2
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
Time Between Conversions
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error3
No Missing Codes
Differential Linearity Error
Transition Noise
Transition Noise
Zero Error, TMIN to TMAX5
Zero Error Temperature Drift
Gain Error, TMIN to TMAX5
Gain Error Temperature Drift
Power Supply Sensitivity
AC ACCURACY
Dynamic Range
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
−3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
INTERNAL REFERENCE
Output Voltage
Temperature Drift
Line Regulation
Turn-On Settling Time
Conditions
VIN+ − VIN−
VIN+, VIN− to AGND
fIN = 100 kHz
2 MSPS throughput
Wideband warp, warp modes
Wideband warp, warp modes
Wideband warp, warp modes
Normal mode
Normal mode
TMIN to TMAX = −40°C to +85°C
VREF = 2.5 V
VREF = 2.048 V
AVDD = 2.5 V ± 5%
VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.5 V
fIN = 20 kHz, VREF = 2.048 V
fIN = 100 kHz, VREF = 2.5 V
Min
16
−VREF
−0.1
0.001
0
−1.5
16
−1
−10
−8
91.5
91
89.5
91
89.5
Full-scale step
PDREF = PDBUF = low
REF @ 25°C
−40°C to +85°C
AVDD = 2.5 V ± 5%
CREF = 10 μF
2.038
Typ Max
+VREF
AVDD1
58
3.5
500
2
1
667
1.5
±0.5 +1.5
+1.25
0.5
0.6
+10
±0.5
+8
±0.5
±4
92.5
92
90.5
91
117
110
101
−115
−109
−100
92
90.5
91
50
1
5
140
2.048
±8
±15
5
2.058
Rev. 0 | Page 3 of 28
AD7622
Unit
Bits
V
V
dB
μA
ns
MSPS
ms
ns
MSPS
LSB4
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
dB6
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
MHz
ns
ps rms
ns
V
ppm/°C
ppm/V
ms

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AD7622 전자부품, 판매, 대치품
AD7622
1 See the Conversion Control section.
2 All timings for wideband warp mode are the same as warp mode.
3 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
4 See the Digital Interface section and the RESET section.
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
Symbol
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK High Minimum
Internal SCLK Low Minimum
SDOUT Valid Setup Time Minimum
t18
t19
t19
t20
t21
t22
SDOUT Valid Hold Time Minimum
t23
SCLK Last Edge to SYNC Delay Minimum
t24
BUSY High Width Maximum
Warp Mode
Normal Mode
t28
t28
0011
0 1 0 1 Unit
3 3 3 3 ns
8 16 32 64 ns
20 40 60 140 ns
2 8 16 32 ns
2 8 16 32 ns
1 5 15 5 ns
0 0.5 10 28 ns
0 0.5 9 26 ns
0.64 0.92 1.47 2.57 μs
0.76 1.04 1.59 2.69 μs
500µA
IOL
TO OUTPUT
PIN CL
50pF
1.4V
500µA
IOH
NOTE
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 3. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 4. Voltage Reference Levels for Timing
Rev. 0 | Page 6 of 28

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