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AD7457 데이터시트 PDF




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부품번호 AD7457 기능
기능 100 kSPS 12-Bit ADC
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AD7457 데이터시트, 핀배열, 회로
Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
Specified for VDD of 2.7 V to 5.25 V
Low power:
0.9 mW max at 100 kSPS with VDD = 3 V
3 mW max at 100 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70 dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface—SPI®-/QSPI™-/
MICROWIRE™-/DSP-compatible
Automatic power-down mode
8-lead SOT-23 package
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GENERAL DESCRIPTION
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
The part contains a low noise, wide bandwidth, differential
track-and-hold (T/H) amplifier that can handle input frequen-
cies in excess of 1 MHz. The reference voltage for the AD7457 is
applied externally to the VREF pin and can range from 100 mV to
VDD, depending on what suits the application.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The SAR architecture of this
part ensures that there are no pipeline delays.
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
VIN
VREF
12-BIT
T/H SUCCESSIVE
APPROXIMATION
ADC
AD7457
CONTROL LOGIC
SCLK
SDATA
CS
GND
Figure 1.
PRODUCT HIGHLIGHTS
1. Operation with 2.7 V to 5.25 V power supplies.
2. Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
3. Pseudo differential analog input.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power consump-
tion to be reduced.
5. Variable voltage reference input.
6. No pipeline delays.
7. Accurate control of the sampling instant via the CS input
and once-off conversion control.
8. ENOB > 10 bits typically with 500 mV reference.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.




AD7457 pdf, 반도체, 판매, 대치품
AD7457
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR)2
Signal to (Noise + Distortion) (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay2
Aperture Jitter2
Full-Power Bandwidth2, 3
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Offset Error2
Gain Error2
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN4
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage5
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN6
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
Test Conditions/Comments
fIN = 30 kHz
−84 dB typ
−86 dB typ
fa = 25 kHz; fb = 35 kHz
@ −3 dB
@ −0.1 dB
B Version1
71
70
−75
−75
−80
−80
5
50
20
2.5
Guaranteed no missed codes to 12 bits
12
±1
±0.95
±4.5
±2
VIN+ − VIN
VREF
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
When in track/hold
VREF
−0.1 to +0.4
−0.1 to +1.5
±1
30/10
±1% tolerance for specified performance
When in track/hold
2.5
±1
10/30
Typically 10 nA, VIN = 0 V or VDD
2.4
0.8
±1
10
VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA
VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA
ISINK = 200 µA
2.8
2.4
0.4
±1
10
Straight natural binary
1.6 µs with a 10 MHz SCLK
See the Serial Interface section
16
1
100
Unit
dB min
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
V
V
V
V
µA max
pF typ
V
µA max
pF typ
V min
V max
µA max
pF max
V min
V min
V max
µA max
pF max
SCLK cycles
µs max
kSPS max
Rev. A | Page 3 of 20

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AD7457 전자부품, 판매, 대치품
AD7457
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VIN+ to GND
VIN– to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Pb-Free Temperature, Soldering
Reflow
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
±10 mA
−40°C to +85°C
−65°C to +150°C
150°C
211.5°C/W (SOT-23)
91.99°C/W (SOT-23)
215°C
220°C
260(+0)°C
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
IOL
1.6mA
TO
OUTPUT
PIN
CL
25pF
1.6V
IOH
200µA
Figure 3. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 6 of 20

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