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PDF ADN4612 Data sheet ( Hoja de datos )
| Número de pieza | ADN4612 | |
| Descripción | 12 x 12 Digital Crosspoint Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
DC to 11.3 Gbps per port, NRZ data rate
Multitime constant, programmable receive equalization
Compensates 25 inches of FR408 at 10.3125 Gbps
Compensates 15 inches of FR408 at 11.3 Gbps
6-tap programmable transmit feedforward equalization (FFE)
Compensates 15 inches of FR408 at 10.3125 Gbps
Compensates 10 inches of FR408 at 11.3 Gbps
Low power
150 mW per channel at 2.5 V (outputs enabled)
12 × 12, fully differential, nonblocking array
Double rank connection programming
2-pin selectable connection maps
Per lane lost of signal (LOS) detection
Flexible output termination supply range (1.8 V to 3.3 V)
DC- or ac-coupled differential CML inputs and outputs
Programmable CML output levels
Load from EEPROM for automatic power-on ready operation
Per lane input and output P/N pair inversion for routing ease
50 Ω on-chip input/output termination
Supports 64-bit/66-bit, scrambled or not coded NRZ data up
to 11.3 Gbps
Serial (I2C or SPI slave) control interface
88-lead LFCSP, 12 mm × 12 mm, Pb-free package
−40°C to +85°C operating temperature range
APPLICATIONS
Fiber optic network switching
10 Gigabit Ethernet over backplane 10GBASE-KR 802.3ap
XLAUI/CAUI (802.3ba)
SONET OC-192/STM-64x
1×, 2×, 4×, 8×, and 10× Fibre Channel
GENERAL DESCRIPTION
The ADN4612 is a 12 × 12 asynchronous, protocol agnostic, digital
crosspoint switch with 12 differential PECL-/CML-compatible
inputs and 12 differential CML outputs.
The ADN4612 is optimized for nonreturn-to-zero (NRZ) signaling
with data rates of up to 11.3 Gbps per port. Each port provides
programmable input equalization, loss of signal (LOS) detection,
programmable output swing, and output preemphasis/deemphasis.
11.3 Gbps, 12 × 12 Digital
Crosspoint Switch
ADN4612
FUNCTIONAL BLOCK DIAGRAM
DVCC
VCC
IP11
TO IP0
Rx
Tx
OP11
TO OP0
VTTIE,
VTTIW
12 × 12
SWITCH
MATRIX
PRE-
EMPHASIS
VTTON,
VTTOS
IN11
EQ
ON11
TO IN0
TO ON0
Rx CONTROL
EQUALIZATION
SIGNAL DETECT
XPT CONTROL
CONNECTIVITY
MAP (A/B/C/D)
SELECT
Tx CONTROL
6-TAP FFE
OUTPUT LEVEL
EEPROM
MAP1, MAP0
RESET
UPDATE
SPI/I2C
SCK/SCL
SDO/SDA
SDI/I2C_A1
CS/I2C_A0
LOS_IRQ
SERIAL
INTERFACE
CONTROL
LOGIC
ADN4612
VEE
Figure 1.
The ADN4612 nonblocking switch core implements a 12 × 12
crossbar and supports independent channel switching through
the serial control interface. The ADN4612 has low latency and
very low channel-to-channel skew.
The ADN4612 is packaged in an 88-lead LFCSP package and
operates from −40°C to +85°C.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADN4612
Data Sheet
SPECIFICATIONS
VCC = VTTO1 = 2.5 V, VTTI2 = V1P8 = DVCC = 1.8 V, VEE = 0 V, RL = 50 Ω, data rate = 11.3 Gbps, data pattern = PRBS 15, ac-coupled inputs
and outputs, differential input swing = 800 mV p-p, EQ setting = 0x12,3 PE boost = 1.94 dB,4 unless otherwise noted.
INPUT/OUTPUT SPECIFICATIONS
Table 1.
Parameter
DYNAMIC PERFORMANCE
Data Rate (NRZ)
Deterministic Jitter (No Channel)
Random Jitter (No Channel)
Residual Deterministic Jitter with
Receive Equalization
Residual Deterministic Jitter with
Transmit Preemphasis
Propagation Delay
Lane-to-Lane Skew
Switching Time
Output Rise/Fall Time
INPUT CHARACTERISTICS
Differential Input Voltage Swing
Input Voltage Range
Differential Input Return Loss (SDD11)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Voltage Setting Resolution
Per Port Output Current
Differential Output Return Loss (SDD22)
TERMINATION CHARACTERISTICS
Resistance
LOS CHARACTERISTICS
Assert Level
Deassert Level
LOS-to-Output Squelch
LOS-to-Output Enable
Test Conditions/Comments
Data rate = 10.3125 Gbps
Data rate = 11.3 Gbps
Input trace = 25-inch FR408, data rate = 10.3125 Gbps,
EQ setting = 0x94
Input trace = 15-inch FR408, data rate = 11.3 Gbps,
EQ setting = 0x72
Output trace = 15-inch FR408, data rate = 10.3125 Gbps,
PE boost = 5.46 dB
Output trace = 10-inch FR408, data rate = 11.3 Gbps,
PE boost = 6.02 dB
50% input to 50% output (maximum EQ)
Signal path and switch architecture is balanced and
symmetric (maximum EQ)
50% logic switching to 50% output data5
20% to 80%, test pattern = 0000000011111111
VICM6 = 1.8 V, VCC = VMIN to VMAX, TA = TMIN to TMAX
Single-ended absolute voltage level, VIL minimum
Single-ended absolute voltage level, VIH maximum
At 2.125 GHz
At 5.5 GHz
Differential; PE boost = 0 dB; default output level, at dc
Single-ended absolute voltage level, VOL
Single-ended absolute voltage level, VOH
Differential absolute voltage level minimum step size,
Tx driver resolution bits = 11b (divide by 8)
PE boost = 0 dB, default output level
At 2.125 GHz
At 5.5 GHz
Differential, VCC = VMIN to VMAX, TA = TMIN to TMAX
Programmable; LOS_ASSERT = 0x2
Programmable; LOS_DEASSERT = 0x6
Time from active signal to idle
Time from idle to active signal
Min
DC
<200
660
90
Typ Max Unit
11.3 Gbps
11 ps p-p
14 ps p-p
0.5 ps rms
0.25 UI
0.25 UI
0.24 UI
0.31 UI
520 ps
±40 ps
10 ns
44 ps
1.0
VCC + 0.3
−24
−10
2000
mV p-p diff
V
V
dB
dB
780
VCC − 1.2
VTTO1
12.5
936
mV p-p diff
V
V
mV p-p diff
16 mA
−20 dB
−9 dB
100 110 Ω
74 mV p-p diff
133 mV p-p diff
1.1 ns
31 ns
1 VTTO is a generic variable that describes both VTTON and VTTOS. VTTON and VTTOS are independent voltages that are not required to equal each other.
2 VTTI is a generic variable that describes both VTTIE and VTTIW. VTTIE and VTTIW are independent voltages that are not required to equal each other.
3 Default EQ setting is used to compensate for loss of test fixture.
4 Default PE setting is used to compensate for loss of test fixture.
5 50% logic level high-to-low transition of the UPDATE toggle pin or 50 % logic level transition of the MAP1 and MAP0 pins while the UPDATE pin is held at logic low.
6 VICM is the input common-mode voltage.
Rev. C | Page 4 of 76
5 Page 
ADN4612
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
VCC to VEE
DVCC to VEE
VTTIE, VTTIW
VTTON, VTTOS
Internal Power Dissipation1
Differential Input Voltage
Logic Input Voltage
Temperature
Storage Temperature Range
Lead Temperature
Junction Temperature
Rating
2.75 V
2.0 V
VCC + 0.6 V
3.6 V
4.9 W
2.0 V
VEE − 0.3 V < VIN < DVCC + 0.6 V
−65°C to +125°C
300°C
125°C
1 Internal power dissipation is for the device in free air. TA = 27°C; θJA = 24.0°C/W
in still air.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Data Sheet
THERMAL RESISTANCE
θJA is specified in still air using a JEDEC 4-layer test board with
the exposed pad soldered. θJC is tested in still air with the thermal
resistance through the exposed pad.
Table 9. Thermal Resistance
Package Type
88-Lead LFCSP
θJA
24.0
θJC
1.7
Unit
°C/W
ESD CAUTION
Rev. C | Page 10 of 76
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADN4612.PDF ] | |
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