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PDF ADG3249 Data sheet ( Hoja de datos )
| Número de pieza | ADG3249 | |
| Descripción | 2:1 Multiplexer/Demultiplexer Bus Switch | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.244 Gbps
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
3.3 V to 2.5 V
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 610 MHz
8-Lead SOT-23 Package
APPLICATIONS
3.3 V to 1.8 V Voltage Translation
3.3 V to 2.5 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Docking Stations
Memory Switching
Analog Switch Applications
2.5 V/3.3 V, 2:1 Multiplexer/
Demultiplexer Bus Switch
ADG3249
FUNCTIONAL BLOCK DIAGRAM
ADG3249
A0
B
A1
CONTROL
LOGIC
IN EN
GENERAL DESCRIPTION
The ADG3249 is a 2.5 V or 3.3 V, high performance 2:1 multi-
plexer/demultiplexer bus switch. It is designed on a low voltage
CMOS process, which provides low power dissipation yet gives
high switching speed and very low on resistance. This allows the
input to be connected to the output without additional propaga-
tion delay or generating additional ground bounce noise.
Each switch of the ADG3249 conducts equally well in both direc-
tions when on. The ADG3249 exhibits break-before-make
switching action, preventing momentary shorting when switch-
ing channels.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from
3.3 V inputs to 2.5 V outputs is allowed. Similarly, if the device
is operated from 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating pin (SEL) is included. When SEL is low, VCC is
reduced internally, allowing for level translating between 3.3 V
inputs and 1.8 V outputs.
The ADG3249 is available in a tiny 8-lead SOT-23 package.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Tiny SOT-23 package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
ADG3249
TERMINOLOGY
VCC
GND
VINH
VINL
II
IOZ
IOL
VP
RON
⌬RON
CX OFF
CX ON
CIN, CSEL, CEN
ICC
⌬ICC
tPLH, tPHL
tPZH, tPZL
tPHZ, tPLZ
tBBM
tTRANS
Max Data Rate
Channel Jitter
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
ON Resistance Match between Any Two Channels, i.e., RON max to RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
Control Input Capacitance. This consists of IN, SEL, and EN.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
Extra power supply current component for the EN control input when the input is not driven at the supplies.
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, EN.
Bus Disable Times. These are the time taken to place the switch in the high impedance OFF state in response to the
control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original
quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable
and disable times.)
On or Off Time. Measured between the 90% points of both switches when switching fom one to another.
Time taken to switch from one channel to the other, measured from 50% of the IN signal to 90% of the
OUT signal.
Maximum Rate at which Data Can Be Passed through the Switch.
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4– REV. 0
5 Page 
ADG3249
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
Multiplexing
Many systems, such as docking stations and memory banks,
have a large number of common bus signals. Common prob-
lems faced by designers of these systems include
• Large delays caused by capacitive loading of the bus
• Noise due to simultaneous switching of the address and data
bus signals
Figure 11 shows an array of memory banks in which each ad-
dress and data signal is loaded by the sum of the individual
loads. If a bus switch is used as shown in Figure 12, the output
load on the memory address and data bits is halved. The speed
at which the selected bank’s data can flow is much improved
because the capacitance loading is halved and the switches
introduce negligible propagation delay. Bus noise is also reduced.
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, EN should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
MEMORY
ADDRESS
MEMORY
BANK A
DATA
MEMORY
BANK B
MEMORY
BANK C
MEMORY
BANK D
Figure 11. All Memory Banks Are Permanently
Connected to the Bus
MEMORY
ADDRESS
MEMORY
BANK A
MEMORY
BANK B
DATA
MEMORY
BANK C
MEMORY
BANK D
Figure 12. ADG3249 Used to Reduce Both Access
Time and Noise
–10–
REV. 0
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADG3249.PDF ] | |
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