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Número de pieza ADRF6612
Descripción 700 MHz to 3000 MHz Dual Passive Receive Mixer
Fabricantes Analog Devices 
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Data Sheet
700 MHz to 3000 MHz Dual Passive
Receive Mixer with Integrated PLL and VCO
ADRF6612
FEATURES
RF frequency: 700 MHz to 3000 MHz, continuous
LO input frequency: 200 MHz to 2700 MHz, high-side or low-
side injection
IF range: 40 MHz to 500 MHz
Power conversion gain of 9.0 dB
Single sideband (SSB) noise figure of 11.3 dB
Input IP3 of 30 dBm
Input P1dB of 10.6 dBm
Typical LO input drive of 0 dBm
Single-ended, 50 Ω RF port
Single-ended or balanced LO input port
Serial port interface (SPI) control on all functions
Exposed pad, 7 mm × 7 mm, 48-lead LFCSP
APPLICATIONS
Multiband/multistandard cellular base station diversity
receivers
Wideband radio link diversity downconverters
Multimode cellular extenders and picocells
FUNCTIONAL BLOCK DIAGRAM
GND 1
2 46
GND 3
VCO
GND 6
VCC1 7 VCO
45 44 48 47 43 42
39 38
PLL REF BUFFER
PFD/CP
FRACTIONAL DIVIDER
VCO
EXTVCOIN+ 4
EXTVCOIN– 5
DECL1 8
DECL2 9
DECL3 10
DECL4 11
DECL5 12
VCO
LDO
SPI
2.5V
LDO
÷1 TO
32
ADRF6612
PLL
3.3V
LDO
DIV
3.3V
LDO
SPI
CONTROL
13 14 15 16 17 18 19
22 23
41 40 37
34 VCC10
33 VCC9
32 VCC8
36 RFBCT1
35 RFIN1
31 VCC7
30 LDO2
26 RFIN2
25 RFBCT2
29 VCC6
28 VCC5
27 VCC4
20 21 24
Figure 1.
GENERAL DESCRIPTION
The ADRF6612 is a dual radio frequency (RF) mixer and
intermediate frequency (IF) amplifier with an integrated phase-
locked loop (PLL) and voltage controlled oscillators (VCOs). The
ADRF6612 uses revolutionary broadband square wave limiting
local oscillator (LO) amplifiers to achieve an unprecedented RF
bandwidth of 700 MHz to 3000 MHz. Unlike narrow-band sine
wave LO amplifier solutions, the LO can be applied above or
below the RF input over an extremely wide bandwidth. Energy
storage elements are not utilized in the LO amplifier, thus dc
current consumption also decreases with decreasing LO
frequency.
The ADRF6612 utilizes highly linear, doubly balanced passive
mixer cores with integrated RF and LO balancing circuits to
allow single-ended operation. Integrated RF baluns allow optimal
performance over the 700 MHz to 3000 MHz RF input frequency.
The balanced passive mixer arrangement provides outstanding
LO to RF and LO to IF leakages, excellent RF to IF isolation,
and excellent intermodulation performance over the full RF
bandwidth.
The balanced mixer cores provide extremely high input
linearity, allowing the device to be used in demanding
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
wideband applications where in band blocking signals may
otherwise result in the degradation of dynamic range. Noise
performance under blocking is comparable to narrow-band
passive mixer designs. High linearity IF buffer amplifiers follow the
passive mixer cores, yielding typical power conversion gains of
9 dB, and can be matched to a wide range of output impedances.
The PLL architecture supports both integer-N and fractional-N
operation and can generate the entire LO frequency range of
200 MHz to 2700 MHz using an external reference input
frequency anywhere in the range of 12 MHz to 320 MHz. An
external loop filter provides flexibility in trading off phase noise
vs. acquisition time. To reduce fractional spurs in fractional-N
mode, a sigma-delta (Σ-Δ) modulator controls the post-VCO
programmable divider. The VCO consists of multiple VCO cores.
All features of the ADRF6612 are controlled via a 3-wire SPI
resulting in optimum performance and minimum external
components.
The ADRF6612 is fabricated using a BiCMOS, high performance
IC process. The device is available in a 7 mm × 7 mm, 48-lead
LFCSP package and operates over a −40°C to +85°C temperature
range. An evaluation board is available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADRF6612 pdf
ADRF6612
Data Sheet
TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, ZO = 50 Ω, fREF = 122.88 MHz, fREF power = 4 dBm, fPFD = 1.536 MHz, low-side LO injection,
optimum RFB and LPF settings, unless otherwise noted.
Table 2. High Efficiency Mode
Parameter
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
Input 1 dB Compression Point (P1dB)
LO to IF Output Leakage
LO to RF Input Leakage
RF to IF Output Isolation
IF/2 Spurious
IF/3 Spurious
POWER INTERFACE
VCC12, VCC7, VCC2, VCC1
Supply Voltage
Quiescent Current
VCC3, VCC4, VCC5, VCC6, VCC8, VCC9,
VCC10, VCC11, IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
Supply Voltage
Quiescent Current
Test Conditions/Comments
Min
4:1 IF port transformer and PCB loss removed
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω
fRF1 = 1900 MHz, fRF2 = 1901 MHz, fLO = 1697 MHz, each
RF tone at −10 dBm
fRF1 = 1900 MHz, fRF2 = 1950 MHz, fLO = 1697 MHz, each
RF tone at −10 dBm
Unfiltered IF output
−10 dBm input power
−10 dBm input power
Typ
8.7
14.7
10.7
20.5
53
8.2
−45.0
−52.0
−22.8
−58
−58
Max Unit
dB
dB
dB
dBm
dBm
dBm
dBm
dBm
dB
dBc
dBc
3.55 3.7
260
3.85 V
mA
3.55 3.7
210
5.25 V
mA
SYNTHESIZER/PLL SPECIFICATIONS
High performance mode, TA = 25°C, measured on LO output, fLO = 1700 MHz, ZO = 50 Ω, fREF =122.88 MHz, fPFD = 1.536 MHz, fREF power =
4 dBm, CSCALE = 8 mA, bleed = 0 µA, ABLDLY = 0.9 ns, integer mode loop filter, unless otherwise noted.
Table 3. Integer Mode
Parameter
SYNTHESIZER SPECIFICATIONS
Frequency Range
Figure of Merit (FOM)1
Phase and Frequency Detector (PFD)
Frequency (fPFD)
Reference Spurs
CHARGE PUMP
Pump Current
Output Compliance Range
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
Reference Divider Value
MUXOUT Output Level
MUXOUT Duty Cycle
Test Conditions/Comments
Synthesizer specifications referenced to 1 × LO
Internally generated LO
PREFIN = 6.5 dBm
fPFD = 1.536 MHz
1 × fPFD
4 × fPFD
>4 × fPFD
Programmable to 250 µA, 500 µA, …, 8 mA
REFIN, MUXOUT pins
Programmable to 0.5, 1, 2, 3, …, 2047
VOL (lock detect output selected)
VOH (lock detect output selected)
Reference output selected
Min Typ Max Unit
200 2700 MHz
−223
dBc/Hz/Hz
0.8 70 MHz
−105
−105
−90
dBc
dBc
dBc
8
0.7
8.75 mA
2.5 V
12
4
0.5
2.7
50
320
2047
0.25
MHz
pF
V
V
%
Rev. A | Page 4 of 57

5 Page





ADRF6612 arduino
ADRF6612
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter
Supply Voltage (VCC1, VCC2, VCC3,
VCC4, VCC5, VCC6, VCC7, VCC8, VCC9,
VCC10, VCC11,VCC12, IFOUT1+,
IFOUT1−, IFOUT2+, IFOUT2−)
Digital Input/Output (SCLK, SDIO, CS)
RFINx
EXTVCOIN+, EXTVCOIN−
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
−0.5 V to +5.5 V
−0.3 V to +3.6 V
20 dBm
13 dBm
150°C
−40°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond the
maximum operating conditions for extended periods may affect
product reliability.
Data Sheet
THERMAL RESISTANCE
θJC is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 9. Thermal Resistance
Package Type
θJC
48-Lead LFCSP
1.62
Unit
°C/W
ESD CAUTION
Rev. A | Page 10 of 57

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