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ADRF5021 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADRF5021은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ADRF5021 기능
기능 Silicon SPDT Switch
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ADRF5021 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Ultrawideband frequency range: 9 kHz to 30 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.0 dB to 30 GHz
High isolation: 60 dB to 30 GHz
High input linearity
1 dB power compression (P1dB): 28 dBm typical
Third-order intercept (IP3): 52 dBm typical
High power handling
24 dBm through path
24 dBm terminated path
ESD sensitivity: Class 1, 1 kV human body model (HBM)
20-terminal, 3 mm × 3 mm land grid array package
No low frequency spurious
Radio frequency (RF) settling time (to 0.1 dB of final RF
output): 6.2 µs
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, electronic counter measures (ECMs)
Broadband telecommunications systems
GENERAL DESCRIPTION
The ADRF5021 is a general-purpose single-pole, double-throw
(SPDT) switch manufactured using a silicon process. It comes
in a 3 mm × 3 mm, 20-terminal land grid array (LGA) package
and provides high isolation and low insertion loss from 9 kHz
to 30 GHz.
9 kHz to 30 GHz,
Silicon SPDT Switch
ADRF5021
FUNCTIONAL BLOCK DIAGRAM
RF2
ADRF5021
RFC
50Ω
50Ω
VSS
EN
CTRL
VDD
RF1
Figure 1.
This broadband switch requires dual supply voltages, +3.3 V
and −2.5 V, and provides CMOS/LVTTL logic-compatible
control.
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADRF5021 pdf, 반도체, 판매, 대치품
Data Sheet
ADRF5021
SPECIFICATIONS
VDD = 3.3 V to 5 V, VSS = −2.5 V, VCTRL = 0 V or 3.3 V to 5 V, VEN = 0 V or 3.3 V to 5 V, TCASE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter
FREQUENCY RANGE
INSERTION LOSS
Between RFC and RF1/RF2
ISOLATION
Between RFC and RF1/RF2
Between RF1 and RF2
RETURN LOSS
RFC and RF1/RF2 (On)
RF1/RF2 (Off )
SWITCHING
Rise and Fall Time
On and Off Time
RF Settling Time
0.1 dB
0.05 dB
INPUT LINEARITY1
Power Compression
0.1 dB
1 dB
Third-Order Intercept
SUPPLY CURRENT
Positive
Negative
DIGITAL CONTROL INPUTS
Voltage
Low
High
Current
Low and High
Symbol Test Conditions/Comments
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to- 30 GHz
9 kHz to 10 GHz
10 GHz to 20 GHz
20 GHz to 30 GHz
tRISE, tFALL
tON, tOFF
10% to 90% of RF output
50% VCTL to 90% of RF output
50% VCTL to 0.1 dB of final RF output
50% VCTL to 0.05 dB of final RF output
1 MHz to 30 GHz
P0.1dB
P1dB
IP3
IDD
ISS
Two-tone input power = 14 dBm each tone,
Δf = 1 MHz
VDD, VSS pins
VDD = 3.3 V
VDD = 5 V
VSS = −2.5 V
CTRL, EN pins
VINL VDD = 3.3 V
VDD = 5 V
VINH VDD = 3.3 V
VDD = 5 V
IINL, IINH
Min Typ Max Unit
0.009
30,000 MHz
1.1 dB
1.4 dB
2.0 dB
65 dB
60 dB
60 dB
70 dB
65 dB
60 dB
23 dB
17 dB
13 dB
30 dB
18 dB
8 dB
1.0 µs
1.1 µs
6.2 µs
10 µs
27 dBm
28 dBm
52 dBm
80 300
100 600
<1 10
µA
µA
µA
0 0.8
0.9
1.2 3.3
1.7 5.0
<1
V
V
V
V
µA
Rev. A | Page 3 of 12

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ADRF5021 전자부품, 판매, 대치품
ADRF5021
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
GND
GND
RFC
GND
GND
20 19 18 17 16
1 15 VSS
2 14 EN
ADRF5021
3
TOP VIEW
13 GND
(Not to Scale)
4 12 CTRL
5 11 VDD
6 7 8 9 10
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF/DC GROUND OF THE PRINTED
CIRCUIT BOARD (PCB).
Figure 5. Pin Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
1, 2, 4 to 7, 9, 10, GND
13, 16, 17, 19, 20
3 RFC
8 RF1
11 VDD
12 CTRL
14 EN
15 VSS
18 RF2
EPAD
Description
Ground. These pins must be connected to the RF/dc ground of the printed circuit board (PCB).
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
Positive Supply Voltage.
Control Input. See Figure 7 for the interface schematic.
Enable Input. See Figure 7 for the interface schematic.
Negative Supply Voltage.
RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
Exposed Pad. The exposed pad must be connected to the RF/dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2
VDD
CTRL, EN
VDD
Figure 6. RFC, RF1, and RF2 Pins Interface Schematic
Figure 7. Digital Pins (CTRL and EN) Interface Schematic
Rev. A | Page 6 of 12

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