PDF HMC1033LP6GE Data sheet ( Hoja de datos )

Número de pieza	HMC1033LP6GE
Descripción	+3.3 V Clock Generator
Fabricantes	Analog Devices
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No Preview Available ! HMC1033LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 550 MHz Typical Applications • 10G/40G/100G Optical Modules, Transponders, Line Cards • OTN and SONET/SDH Applications • Data Converters, Sample Clock Generation • Cellular/4G Infrastructure • High Frequency Processor/FPGA Clocks • Any Frequency Clock Rate Generation • Low Jitter SAW Oscillator Replacement • DDS Replacement • Frequency Translation • Frequency Margining Functional Diagram Features 3.3 V Only, Single Supply Rail Operation Output Frequency Range: 25 MHz - 550 MHz Integer or Fractional-N mode Frequency Translation Configurable LVDS-compatible or LVPECL type Differential Outputs “Power Priority” and“Performance Priority” modes 99 fs RMS Jitter Generation (12 kHz - 20 MHz, 550 MHz, Typ) -163 dBc/Hz Phase Noise Floor to Improve ADC/DAC SNR (maximum output swing levels). Adjustable PLL Loop BW via External Filter Output Disable/Mute Control Lock Detect Signal Exact Frequency Mode to achieve reference frequency tuning, and 0 Hz frequency error 40 Lead 6x6 mm SMT Package: 36 mm2 InfoFrmoartiopnrfiucrneis,heddeblyivAenraylogaDnedvicteos ips lbaelcieevedortodbeersac:cHuraittetiatend Mreliiacbrleo. wHoawveeverC, noorpoForar tpioricne,, 2deElilviezrayb, aentdh tDo rpivlaec,eCohrdeelrms:sAfonardlo,gMDAevi0ce1s8,2In4c., 1 responsibility rights of third pisaartsiessumtheadt mbyaPyArhneasoluonlgt feDro:emv9icit7ess8ufso-er2.itS5spu0esc-eif3,icn3aotri4ofno3sr asnuybjienFcfrtaintoxgec:mh9aenn7gts8e ow-f2ipth5aotue0tn-nts3ooti3cr eo7.th3Neor lTicraednesemaisrkgsraanndtedregbiysteimrepdlictraatdioenmoarrkosthaerArewtpihseeppulrniocdpeearrttyainooyfntphaeStier nuret psoprpepcoativtreetn:ot wrPignehhrtsso. onf eA:na9lo7g 8D-ev2ic5es0. - 3OPA3Ohpn4rope3dnliTeece:aorc7trihO8on1nnao-S3lp-ol2ugpi9npys-pe4W@o7ara0hty:t0i,Ptw•Pthi.wOtoOenr.w.decB:e.oo1hr x-moi8tn9t0l1ii0tn0e-e6A.,caNNtoAwomLrwOwwGoo.-adDn,aMloAg.0c2o0m62-9106 1 page HMC1033LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 550 MHz Electrical Specifications (Continued) Parameter Power Supply Voltages + 3.3V Supplies Power Supply Currents +3.3V Power Down - Crystal Off Power Down - Crystal On, 100 MHz Power on Reset Typical Reset Voltage on DVDD Minimum DVDD Voltage for No Reset Power on Reset Delay Figure of Merit Floor Integer Mode Floor Fractional Mode Flicker (Both Modes) Phase Jitter RMS, Integer Mode Phase Jitter RMS, Fractional Mode Condition AVDD, VPPCP, VDDLS,3VRVDD, DVDD3V, VCC1, VCC2, VCCHF, VCCPS, VCCPD LVPECL, Performance Priority Mode, 350 MHz output, Excluding Load LVPECL Performance Prior- ity Mode, 350 MHz output, Includes Termination LVPECL Performance Priority Mode, 155.52 MHz Output, Includes Termination LVDS, Power Priority Mode, 350 MHz Output, Includes Termination LVDS, Power Priority Mode, 155.52 MHz Output, Includes Termination Reg 01h=0, Crystal Not Clocked Reg 01h=0, Crystal Clocked 100 MHz Min. 3.15 1.5 Normalized to 1 Hz Normalized to 1 Hz Normalized to 1 Hz 155.52 MHz Output , 12 kHz to 20 MHz 350 MHz Output 12 kHz -20MHz 155.52 MHz Output , 12 kHz to 20 MHz 350 MHz Output 12 kHz -20MHz Typ. Max. Units 3.3 3.5 V 208 240 242 195 197 10 5 700 250 -227 -226 -268 107 99 122 124 mA mA mA mA mA µA mA mV V µs dBc/Hz dBc/Hz dBc/Hz fs fs fs fs [1] Measurements made are AC coupled into a 100 differential load (Except Phase Noise). [2] The maximum phase detector frequency can only be achieved if the minumum N value is respected, eg in the case of fractional feedback mode, the maximum PFD rate = fvco/20 or 100 MHz whichever is less. Operation > 70MHz may require offsett currents to be disabled and reenabled. InfoFrmoartiopnrfiucrneis,heddeblyivAenraylogaDnedvicteos ips lbaelcieevedortodbeersac:cHuraittetiatend Mreliiacbrleo. wHoawveeverC, noorpoForar tpioricne,, 2deElilviezrayb, aentdh tDo rpivlaec,eCohrdeelrms:sAfonardlo,gMDAevi0ce1s8,2In4c., responsibility rights of third pisaartsiessumtheadt mbyaPyArhneasoluonlgt feDro:emv9icit7ess8ufso-er2.itS5spu0esc-eif3,icn3aotri4ofno3sr asnuybjienFcfrtaintoxgec:mh9aenn7gts8e ow-f2ipth5aotue0tn-nts3ooti3cr eo7.th3Neor lTicraednesemaisrkgsraanndtedregbiysteimrepdlictraatdioenmoarrkosthaerArewtpihseeppulrniocdpeearrttyainooyfntphaeStier nuret psoprpepcoativtreetn:ot wrPignehhrtsso. onf eA:na9lo7g 8D-ev2ic5es0. - 3OPA3Ohpn4rope3dnliTeece:aorc7trihO8on1nnao-S3lp-ol2ugpi9npys-pe4W@o7ara0hty:t0i,Ptw•Pthi.wOtoOenr.w.decB:e.oo1hr x-moi8tn9t0l1ii0tn0e-e6A.,caNNtoAwomLrwOwwGoo.-adDn,aMloAg.0c2o0m62-9106 4 5 Page Evaluation PCB HMC1033LP6GE v01.0712 High Performance, +3.3 V Clock Generator 25 - 550 MHz The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. The HMC1033 evaluation board and associated software offers the user an easy way to quickly evaluate the performance and flexibility of the HMC1033. The evaluation board operates off a +5V supply and includes an HMC1060 LDO, which generates a low noise 3.3V source, and a precision PLL which generates a 50MHz clock, which is locked to an externally supplied 10 MHz reference. The PLL design is an HMC1031 phase/frequency detector, passive loop filter and a low noise 50 MHz VCXO. The PLL is normally, or default upon shipping, set to lock on to a 10 MHz reference feed into “REF IN”. A 5MHz input reference can be used if D1, D0 is reconfigured to “1,1”, or 50 MHz if D1, D0 is reconfigured to “0,1”. The “REF IN” would normally have a +/-50 ppm tolerance which falls within the VCXO pull range. Although not recommended, the HMC1033 EB can be operated without supplying an external reference, and the PLL will pull the VCXO to about 49.992 MHz, or 180 ppm low. Alternatively, an external 50 MHz reference can be feed into the HMC1033 evaluation board which requires removing C44,C35, R32 and J6, the TPLL/TCXO, and placing a 0 Ohm resistor in the R20 and R36 locations. Evaluation PCB Schematic To view this Evaluation PCB Schematic please visit www.hittite.com and choose HMC1033LP6GE from the “Search by Part Number” pull down menu to view the product splash page. Evaluation Order Information Item Evaluation PCB Only Evaluation Kit Contents HMC10333LLPP66GGEEvEavluaalutiaotnioPnCPBCB HMC1033LP6GGEEvEavluaalutiaotnioPnCPBCB USB Interface Board 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software, Hittite PLL Design Software) Part Number EVA0L10-1H-MHCM1C013033L3PL6PG6GE EKIT011--HHMMCC11003333LLPP66GGE InfoFrmoartiopnrfiucrneis,heddeblyivAenraylogaDnedvicteos ips lbaelcieevedortodbeersac:cHuraittetiatend Mreliiacbrleo. wHoawveeverC, noorpoForar tpioricne,, 2deElilviezrayb, aentdh tDo rpivlaec,eCohrdeelrms:sAfonardlo,gMDAevi0ce1s8,2In4c., responsibility rights of third pisaartsiessumtheadt mbyaPyArhneasoluonlgt feDro:emv9icit7ess8ufso-er2.itS5spu0esc-eif3,icn3aotri4ofno3sr asnuybjienFcfrtaintoxgec:mh9aenn7gts8e ow-f2ipth5aotue0tn-nts3ooti3cr eo7.th3Neor lTicraednesemaisrkgsraanndtedregbiysteimrepdlictraatdioenmoarrkosthaerArewtpihseeppulrniocdpeearrttyainooyfntphaeStier nuret psoprpepcoativtreetn:ot wrPignehhrtsso. onf eA:na9lo7g 8D-ev2ic5es0. - 3OPA3Ohpn4rope3dnliTeece:aorc7trihO8on1nnao-S3lp-ol2ugpi9npys-pe4W@o7ara0hty:t0i,Ptw•Pthi.wOtoOenr.w.decB:e.oo1hr x-moi8tn9t0l1ii0tn0e-e6A.,caNNtoAwomLrwOwwGoo.-adDn,aMloAg.0c2o0m62-9106 10 11 Page

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