Datasheet.kr   

AD9518-0 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 AD9518-0은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 AD9518-0 자료 제공

부품번호 AD9518-0 기능
기능 6-Output Clock Generator
제조업체 Analog Devices
로고 Analog Devices 로고


AD9518-0 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

AD9518-0 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
3 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9518-01 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz
to 2.95 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9518-0 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
The AD9518-0 features six LVPECL outputs (in three pairs).
The LVPECL outputs operate to 1.6 GHz.
For applications that require additional outputs, a crystal
reference input, zero-delay, or EEPROM for automatic
configuration at startup, the AD9520 and AD9522 are available.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
6-Output Clock Generator with
Integrated 2.8 GHz VCO
AD9518-0
FUNCTIONAL BLOCK DIAGRAM
CP LF
REFIN
REF1
REF2
STATUS
MONITOR
VCO
CLK
DIVIDER
AND MUXs
DIV/Φ
DIV/Φ
DIV/Φ
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
LVPECL
LVPECL
LVPECL
AD9518-0
Figure 1.
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
In addition, the AD9516 and AD9517 are similar to the AD9518
but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide ratio
and coarse delay (or phase) to be set. The range of division for
the LVPECL outputs is 1 to 32.
The AD9518-0 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-0 is specified for operation over the industrial
range of −40°C to +85°C.
1 AD9518 is used throughout the data sheet to refer to all the members of
the AD9518 family. However, when AD9518-0 is used, it refers to that specific
member of the AD9518 family.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.




AD9518-0 pdf, 반도체, 판매, 대치품
Data Sheet
REVISION HISTORY
1/12—Rev. B to Rev. C
Change to 0x232 Description, Table 49........................................58
9/11—Rev. A to Rev. B
Changes to Applications and General Description Sections.......1
Change to CPRSET Pin Resistor Parameter, Table 1....................4
Changes to Table 2 ............................................................................4
Change to Test Conditions/Comments Column of Output
Differential Voltage (VOD) Parameter, Table 4 ...............................5
Change to Logic 1 Current and Logic 0 Current Parameters,
Table 14.............................................................................................10
Change to Test Conditions/Comments Column of LVPECL
Channel (Divider Plus Output Driver) Parameter, Table 16 .....11
Changes to Table 19 ........................................................................14
Changes to Captions, Figure 11 and Figure 16............................17
Added Figure 26, Renumbered Sequentially ...............................19
Change to PLL External Loop Filter Section...............................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to Comments/Conditions Column, Table 27 ..............29
Changes to Automatic/Internal Holdover Mode and
Frequency Status Monitors Sections.............................................32
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Write Section.................................................................40
Change to Figure 47 ........................................................................42
Changes to Table 41 ........................................................................44
Changes to Register Address 0x01C, Table 42 ............................45
Changes to Register Address 0x017, Bits[1:0] and
Register Address 0x018, Bits[2:0], Table 44 .................................50
Changes to Register Address 0x01C, Bits[5:1], Table 44............53
Change to Bit 5, Register Address 0x191, Register
Address 0x194, and Register Address 0x197, Table 46...............56
Changes to LVPECL Clock Distribution Section .......................60
Updated Outline Dimensions and Changes to
Ordering Guide ...............................................................................61
1/10—Rev. 0 to Rev. A
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal
AD9518-0
Changes to Features, Applications, and General Description.....1
Change to CPRSET Pin Resistor Parameter..................................4
Changes to VCP Supply Parameter.................................................11
Changes to Table 18 ........................................................................13
Added Exposed Paddle Notation to Figure 4;
Changes to Table 19 ........................................................................14
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 21..........22
Changes to Table 23 ........................................................................24
Change to Configuration and Register Settings Section ...........25
Change to Phase Frequency Detector (PFD) Section ................26
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........27
Change to Figure 31; Added Figure 32.........................................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to A and B Counters Section and Table 27 ..................29
Change to Holdover Section..........................................................31
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Table 32; Change to Channel Frequency
Division (0, 1, and 2) Section ........................................................35
Change to Write Section ................................................................40
Change to Figure 46........................................................................42
Added Thermal Performance Section; Added Table 41 ............44
Changes to 0x003 Register Address..............................................45
Changes to Table 43 ........................................................................47
Changes to Table 44 ........................................................................48
Changes to Table 45 ........................................................................55
Changes to Table 46 ........................................................................57
Changes to Table 47 ........................................................................58
Changes to Table 48 ........................................................................59
Added Frequency Planning Using the AD9518 Section............60
Changes to LVDS Clock Distribution Section ............................61
Changes to Figure 52 and Figure 54; Added Figure 53..............61
Added Exposed Paddle Notation to Outline Dimensions;
Changes to Ordering Guide...........................................................62
8/07—Revision 0: Initial Version
Rev. C | Page 3 of 64

4페이지










AD9518-0 전자부품, 판매, 대치품
AD9518-0
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Input Sensitivity, Differential
Min Typ Max Unit
01 2.4 GHz
01 1.6 GHz
150 mV p-p
Input Level, Differential
2 V p-p
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1.3
1.3
3.9
1.57 1.8
1.8
150
4.7 5.7
2
V
V
mV p-p
kΩ
pF
1 Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min Typ Max Unit
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
2950
MHz
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
VS_LVPECL
1.12
VS_LVPECL
2.03
550
VS_LVPECL
0.98
VS_LVPECL
1.77
790
VS_LVPECL
0.84
VS_LVPECL
1.49
980
V
V
mV
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 16 for peak-to-peak
differential amplitude
This is VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling; the
peak-to-peak amplitude measured using a differential
probe across the differential pair with the driver toggling
is roughly 2× these values (see Figure 16 for variation
over frequency)
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL,
CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution
Configuration
Clock Distribution Configuration
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS1
LVPECL Outputs That Share the
Same Divider
LVPECL Outputs on Different
Dividers
All LVPECL Outputs Across Multiple
Parts
Min
835
773
Typ Max Unit Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
70 180 ps 20% to 80%, measured differentially
70 180 ps 80% to 20%, measured differentially
995
1180
ps
See Figure 28
933
1090
ps
See Figure 30
0.8 ps/°C
5 15 ps
13 40
ps
220 ps
1 This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Rev. C | Page 6 of 64

7페이지


구       성 총 30 페이지수
다운로드[ AD9518-0.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
AD9518-0

6-Output Clock Generator

Analog Devices
Analog Devices
AD9518-1

6-Output Clock Generator

Analog Devices
Analog Devices

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵