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PDF ADF4169 Data sheet ( Hoja de datos )
| Número de pieza | ADF4169 | |
| Descripción | Fractional-N Frequency Synthesizer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Direct Modulation/Fast Waveform Generating,
13.5 GHz, Fractional-N Frequency Synthesizer
ADF4169
FEATURES
GENERAL DESCRIPTION
RF bandwidth to 13.5 GHz
The ADF4169 is a 13.5 GHz, fractional-N frequency synthesizer
High and low speed FMCW ramp generation
25-bit fixed modulus allows subhertz frequency resolution
PFD frequencies up to 130 MHz
Normalized phase noise floor of −224 dBc/Hz
FSK and PSK functions
Sawtooth and triangular waveform generation
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp delay, frequency readback, and interrupt functions
Programmable phase control
2.7 V to 3.45 V analog power supply
1.8 V to 2 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
ESD performance: 3000 V HBM, 1000 V CDM
Qualified for automotive applications
APPLICATIONS
FMCW radars
Communications test equipment
Communications infrastructure
with modulation and both fast and slow waveform generation
capability. The device uses a 25-bit fixed modulus, allowing
subhertz frequency resolution.
The ADF4169 consists of a low noise digital phase frequency
detector (PFD), a precision charge pump, and a programmable
reference divider. The Σ-Δ-based fractional interpolator allows
programmable fractional-N division. The INT and FRAC registers
define an overall N divider as N = INT + (FRAC/225).
The ADF4169 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. Frequency sweep
modes are also available to generate various waveforms in the
frequency domain, for example, sawtooth waveforms and
triangular waveforms. Sweeps can be set to run automatically
or with each step manually triggered by an external pulse. The
ADF4169 features cycle slip reduction (CSR) circuitry, which
enables faster lock times without the need for modifications to
the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The
ADF4169 operates with an analog power supply in the range of
2.7 V to 3.45 V and a digital power supply in the range of 1.8 V
to 2 V. The device can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD SDVDD
VP
RSET
ADF4169
REFIN
MUXOUT
CE
TXDATA
×2
DOUBLER
5-BIT
R COUNTER
÷2
DIVIDER
HIGH-Z
OUTPUT
MUX
DGND
SERIAL DATA
OUTPUT
DVDD
R DIVIDER/2
N DIVIDER/2
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
+ PHASE
FREQUENCY
DETECTOR
–
REFERENCE
CHARGE
PUMP
CSR
FAST LOCK
SWITCH
SW2
CP
SW1
N COUNTER
+
–
RFINA
RFINB
CLK
DATA
LE
32-BIT
DATA
REGISTER
FRACTION MODULUS
VALUE 225 VALUE
INTEGER
VALUE
AGND DGND
SDGND
Figure 1.
CPGND
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADF4169
Data Sheet
Parameter1
NOISE CHARACTERISTICS
Normalized Phase Noise Floor3
Integer-N Mode
Fractional-N Mode
Normalized 1/f Noise (PN1_f)4
Phase Noise Performance5
12,002 MHz Output6
Min Typ Max Unit Test Conditions/Comments
−224
−217
−120
−96
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase-locked loop (PLL) bandwidth (BW) =
1 MHz
FRAC = 0; see Σ-Δ Modulator Mode section
Measured at 10 kHz offset, normalized
to 1 GHz
At the voltage controlled oscillator (VCO)
output
At 50 kHz offset, 100 MHz PFD frequency
1 Operating temperature: −40°C to +125°C.
2 Guaranteed by design. Sample tested to ensure compliance.
3 This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(fPFD) + 20 logN) to calculate
in-band phase noise performance as seen at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at an offset frequency (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.
5 The phase noise performance is measured with a modified EV-ADF4159EB3Z evaluation board and the Rohde & Schwarz® FSUP signal source analyzer.
6 fREFIN = 100 MHz, fPFD = 100 MHz, offset frequency = 50 kHz, RFOUT = 12,002 MHz, N = 120.02, and loop bandwidth = 250 kHz.
TIMING SPECIFICATIONS
AVDD = VP = 2.7 V to 3.45 V, DVDD = SDVDD = 1.9 V, AGND = DGND = SDGND = CPGND = 0 V, TA = TMIN to TMAX, dBm referred to 50 Ω,
unless otherwise noted.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX
t1 20
t2 10
t3 10
t4 25
t5 25
t6 10
t7 20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
CLK
t4 t5
DATA
DB31 (MSB)
t1
LE
t2 t3
DB30
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
Figure 2. Write Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. 0 | Page 4 of 36
5 Page 
ADF4169
THEORY OF OPERATION
REFERENCE INPUT SECTION
Figure 18 shows the reference input stage. The SW1 and SW2
switches are normally closed (NC in Figure 18). The SW3
internal switch is normally open (NO in Figure 18). When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. In this way, no loading of the REFIN pin occurs during
power-down.
POWER-DOWN
CONTROL
NC 100kΩ
REFIN NC
SW2
SW1
SW3
NO
TO R COUNTER
BUFFER
Figure 18. Reference Input Stage
RF INPUT STAGE
Figure 19 shows the RF input stage. The input stage is followed
by a two-stage limiting amplifier to generate the current-mode
logic (CML) clock levels required for the prescaler.
BIAS
GENERATOR
1.6V
2kΩ 2kΩ
AVDD
RFINA
RFINB
Figure 19. RF Input Stage
AGND
RF INT DIVIDER
The RF INT CMOS divider allows a division ratio in the PLL
feedback counter (see Figure 20). Division ratios from 23 to
4095 are allowed.
RF INT DIVIDER
FROM RF
INPUT STAGE
N COUNTER
N = INT + FRAC/MOD
TO PFD
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
VALUE
MOD
VALUE
FRAC
VALUE
Data Sheet
25-BIT FIXED MODULUS
The ADF4169 has a 25-bit fixed modulus. This modulus allows
output frequencies to be spaced with a resolution of
fRES = fPFD/225
(1)
where fPFD is the frequency of the phase frequency detector (PFD).
For example, with a PFD frequency of 100 MHz, frequency
steps of 2.98 Hz are possible. Due to the architecture of the Σ-Δ
modulator, there is a fixed +(fPFD/226) offset on the VCO output.
To remove this offset, see the Σ-Δ Modulator Mode section.
INT, FRAC, AND R COUNTER RELATIONSHIP
The INT and FRAC values, in conjunction with the R counter,
make it possible to generate output frequencies that are spaced
by fractions of the PFD frequency.
The RF VCO frequency (RFOUT) equation is
RFOUT = (INT + (FRAC/225)) × fPFD
(2)
where:
RFOUT is the output frequency of the external VCO.
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
FRAC is the numerator of the fractional division (0 to (225 − 1)).
The PFD frequency (fPFD) equation is
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
(3)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference (R) counter (1 to 32).
T is the REFIN divide by 2 bit (0 or 1).
R COUNTER
The 5-bit R counter allows the reference input (REFIN) frequency
to be divided down to supply the reference clock to the PFD.
Division ratios from 1 to 32 are allowed.
Figure 20. RF INT Divider
Rev. 0 | Page 10 of 36
11 Page | ||
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