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ADF4196 데이터시트 PDF




Analog Devices에서 제조한 전자 부품 ADF4196은 전자 산업 및 응용 분야에서
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부품번호 ADF4196 기능
기능 6 GHz PLL Frequency Synthesizer
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ADF4196 데이터시트, 핀배열, 회로
Data Sheet
Low Phase Noise, Fast Settling, 6 GHz
PLL Frequency Synthesizer
ADF4196
FEATURES
Fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled
within 20 μs
1 degree rms phase error at 4 GHz RF output
Digitally programmable output phase
RF input range up to 6 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz
APPLICATIONS
GSM/EDGE base stations
PHS base stations
Pulse Doppler radar
Instrumentation and test equipment
Beam-forming/phased array systems
GENERAL DESCRIPTION
The ADF4196 frequency synthesizer can be used to implement
local oscillators (LO) in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time require-
ments for base stations, and the fast settling feature makes the
ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency
detector (PFD) and a precision differential charge pump.
A differential amplifier converts the differential charge pump
output to a single-ended voltage for the external voltage controlled
oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter-
polator, working with the N divider, allows programmable modulus
fractional-N division. Additionally, the 4-bit reference (R) counter
and on-chip frequency doubler allow selectable reference signal
(REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a VCO. The
switching architecture ensures that the PLL settles within the
GSM time slot guard period, removing the need for a second
PLL and associated isolation switches. This decreases the cost,
complexity, PCB area, shielding, and characterization found on
previous ping-pong GSM PLL architectures.
FUNCTIONAL BLOCK DIAGRAM
SDVDD DVDD1 DVDD2 DVDD3 AVDD
VP1 VP2 VP3
RSET
REFIN
MUXOUT
CLK
DATA
LE
×2
DOUBLER
HIGH-Z
OUTPUT
MUX
24-BIT
DATA
REGISTER
4-BIT R
COUNTER
/2
DIVIDER
VDD
DGND
LOCK DETECT
RDIV
NDIV
FRACTIONAL
INTERPOLATOR
REFERENCE
+ PHASE
FREQUENCY
DETECTOR
CHARGE +
PUMP
DIFFERENTIAL
AMPLIFIER
+
N COUNTER
FRACTION MODULUS
REG
REG
INTEGER
REG
ADF4196
SW1
CPOUT+
CPOUT–
SW2
CMR
AIN–
AIN+
AOUT
SW3
RFIN+
RFIN–
AGND1
AGND2
DGND1
DGND2
Figure 1.
DGND3 SDGND SWGND
Rev. D
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF4196 pdf, 반도체, 판매, 대치품
Data Sheet
ADF4196
SPECIFICATIONS
AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V;
RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range = −40°C to +85°C.
Table 1.
Parameter
RF CHARACTERISTICS
RF Input Frequency (RFIN±)
RF Input Sensitivity
Maximum Allowable Prescaler Output
Frequency1
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Edge Slew Rate
REFIN Input Sensitivity
Min
0.4
−10
300
0.7
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency
CHARGE PUMP
ICP Up/Down
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP Up vs. Down Matching
ICP vs. VCP
ICP vs. Temperature
DIFFERENTIAL AMPLIFIER
Input Current
Output Voltage Range
VCO Tuning Range
Output Noise
LOGIC INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IINH, IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
DVDD1, DVDD2, DVDD3
VP1, VP2
VP3
IDD (AVDD + DVDD1, DVDD2, DVDD3 +
SDVDD)
IDD (VP1 + VP2)
IDD (VP3)
IDD Power-Down
1
1.4
1.8
1.4
VDD − 0.4
2.7
4.5
5.0
Typ
6.6
104
5
1
0.1
1
1
1
7
AVDD
22
22
24
10
Max Unit Test Conditions/Comments
6 GHz See Figure 21 for input circuit
0 dBm
750 MHz
300
VDD
0 to VDD
10
±100
26
MHz
V/µs
V p-p
V
pF
µA
MHz
For f > 120 MHz, set REF/2 bit = 1 (Register R1)
AC-coupled
CMOS compatible
4
VP3 − 0.3
VP3 − 0.8
mA RSET = 2.4 kΩ
µA RSET = 2.4 kΩ
%
kΩ Nominally RSET = 2.4 kΩ
nA
% 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
% 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
% 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V
nA
V
V
nV/√Hz
At 20 kHz offset
V
0.7 V
±1 µA
10 pF
V IOH = 500 µA
0.4 V IOL = 500 µA
3.3 V
V
5.5 V AVDD ≤ VP1, VP2 ≤ 5.5 V
5.65 V VP1, VP2 ≤ VP3 ≤ 5.65 V
27 mA
27 mA
30 mA
µA
Rev. D | Page 3 of 28

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ADF4196 전자부품, 판매, 대치품
ADF4196
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
PIN 1
INDICATOR
CMR 1
AOUT 2
SW3 3
AGND1 4
RFIN– 5
RFIN+ 6
AVDD 7
DVDD1 8
ADF4196
TOP VIEW
(Not to Scale)
24 VP2
23 RSET
22 AGND2
21 DGND3
20 VP1
19 LE
18 DATA
17 CLK
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 CMR Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to
three-fifths of VP3. Requires a 0.1 µF capacitor to the ground plane.
2 AOUT
Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.
3 SW3
Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active.
4
AGND1
Analog Ground. This is the ground return pin for the differential amplifier and the RF section.
5 RFIN− Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
6 RFIN+ Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.
7 AVDD Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as
close as possible to this pin.
8
DVDD1
Power Supply Pin for the N Divider. DVDD1 should be at the same voltage as AVDD. Place a 0.1 µF decoupling
capacitor to the ground plane as close as possible to this pin.
9
DGND1
Ground Return Pin for DVDD1.
10 DVDD2 Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the
ground plane as close as possible to this pin.
11 REFIN
Reference Input. This CMOS input has a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
12 DGND2
Ground Return Pin for DVDD2 and DVDD3.
13 DVDD3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
14 SDGND
Ground Return Pin for the Digital Σ-Δ Modulator.
15 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground
plane as close as possible to this pin.
16
MUXOUT
Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally (see Figure 35 for details).
17 CLK
Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
18 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
19 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is
selected by the three LSBs.
20 VP1
Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, VP1 should be at the same voltage as VP2.
Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.
21 DGND3
22 AGND2
Ground Return Pin for VP1.
Ground Return Pin for VP2.
Rev. D | Page 6 of 28

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