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HMC703LP4E 데이터시트 PDF




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부품번호 HMC703LP4E 기능
기능 8 GHz fractional synthesizer
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HMC703LP4E 데이터시트, 핀배열, 회로
v02.0813
Typical Applications
The HMC703LP4E is ideal for:
Microwave Point-to-Point Radios
Base Stations for Mobile Radio
(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, WiMAX
Communications Test Equipment
CATV Equipment
Automotive Sensors
AESA - Phased Arrays
FMCW Radar Systems
HMC703LP4E
8 GHz fractional synthesizer
Features
Wide band: DC - 8 GHz RF Input
Best Phase Noise and Spurious in the Industry:
-112 dBc/Hz @ 8 GHz Fractional, 50 kHz Offset
Figure of Merit
-230 dBc/Hz Fractional Mode
-233 dBc/Hz Integer Mode
High PFD rate: 100 MHz
< 50 fs RMS jitter
Frequency and Phase Modulation
Integrated Frequency Sweeper
Triggered Frequency Hopping
External Triggering
24 Lead 4x4 mm SMT Package: 16 mm2
Functional Diagram
General Description
The HMC703LP4E fractional synthesizer is built upon
the high performance PLL platform also contained in
the HMC704LP4E and Hittite’s latest generation of
PLL+VCO products. This platform has the best phase-
noise and spurious performance in the industry -
enabling higher order modulation schemes while
minimizing blocker effects in high performance radios.
In addition, the HMC703LP4E offers frequency sweep
and modulation features, external triggering, double-
buffering, exact frequency control, phase modulation
and more - while maintaining pin compatibility with the
HMC700LP4E PLL.
Exact frequency mode with a 24-bit fractional mod­
ulator provides the ability to generate fractional
frequencies with zero frequency error and very low
channel spurious, an important feature for Digital Pre-
Distortion systems.
The serial interface offers read back capability and is
compatible with a wide variety of protocols.
6-1
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HMC703LP4E pdf, 반도체, 판매, 대치품
v02.0813
HMC703LP4E
8 GHz fractional synthesizer
6-3
Table 34. Electrical Specifications (Continued)
Parameter
PHASE NOISE [14]
Flicker Figure of Merit (FOM)[2]
Floor Figure of Merit [11]
Flicker Noise at foffset
Phase Noise Floor at fvco with fpd
VCO referred Phase Noise Contribution
of the PLL vs foffset, fvco, fpd
Jitter
SPURIOUS
Integer Boundary Spurs @~8GHz
LOGIC INPUTS
Switching Theshold (Vsw)
LOGIC OUTPUT
VOH Output High Voltage
VOL Output Low Voltage
Output impedance : Pull Up
Output impedance : Pull Dn
Conditions
Min.
Integer HiK Mode
Integer Normal Mode
Fractional HiK Mode [3]
Fractional Normal Mode [3]
-236
-232
-232
-228
PNflick = Flicker FOM +20log(fvco) -10log(foffset)
PNfloor = Floor FOM + 10log(fpd) +20log(fvco/fpd)
PN = 10log(10(PNflick /10) + 10(PNfloor /10) )
SSB 100Hz to 100MHz with
HMC508LP5E VCO
[4][5]
offsets less than loop band-
width, fpd = 50MHz
VIH/VIL within 50 mV of Vsw
38
VDDIO=3.3 V
VDDIO=3.3 V
115
130
Typ.
-270
-233
-230
-230
-227
50
-60
47
VDDIO
0
150
135
DC load
Digital Output Driver Delay
SCK to Digital Output Delay
1.7nsec with a 3 pF load
0.5ns+0.2ns/pF
8.2ns+0.2ns/pF
RF Divider Range
>4GHz Integer Mode
< 4GHz Integer Mode
> 4GHz Fractional Mode
< 4GHz Fractional Mode
16 bit , Even values only
16 bit , All values
16 bit
16 bit
32
16
40.0
20.0
Max.
-231
-228
-227
-225
-52
54
180
210
1.5
131,070
65,535
131,065.0
65,531.0
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
% VDDIO
V
V
Ohm
Ohm
mA
ns
ns
[1] Frequency is guaranteed across process, voltage and temperature from -400C to 850C.
[2] With high charge-pump current, +12dBm 100MHz sine reference
[3] Fractional FOM degrades about 3dB/octave for prescaler input frequencies below 2GHz
[4] Using 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger
offsets produce better results. See the “Spurious Performance” section for more information.
[5] Measured with the HMC703LP4E evaluation board. Board design and isolation will affect performance.
[6] Internal divide-by-2 should be enabled for frequencies >4GHz
[7] At low RF Frequency, Rise and fall times should be less than 1ns to maintain performance
[8] Slew rate of greater or equal to 0.5 V/ns
[9] Current consumption depends upon operating mode and frequency of the VCO. Typical values are for fractional mode.
[10] Reference input disconnected
[11] Min/Max versus temperature and supply, under typical reference & RF frequencies and power levels
[12] Slew > 0.5V/ns is recommended , see Table 7, Figure 5, Figure 6 for more information.
[13] Operable with reduced spectral performance outside of this range.
[14] This section specifies the Phase Noise contribution of the PLL, solution phase noise with a given VCO, loop filter and
reference requires a closed loop calculation using Hittite PLL Design Tool.
[15] As measured on HMC703LP4E Evaluation board, with 100Ohm external termination.
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HMC703LP4E 전자부품, 판매, 대치품
v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Figure 13. Typical Phase Noise & Spur
Performance at 8 GHz + 200 kHz[3]
-60
Figure 14. Fractional Performance, Exact
Frequency Mode On at 8013.6 MHz [4]
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
-180
102 103 104 105 106 107 108
OFFSET(Hz)
Figure 15. Integer Boundary Spur at
8 GHz + 20 kHz vs. Charge Pump Offset[5]
-20
20 kHz Offset Spur
-30 10 kHz Offset Spur
Recommended
-40 Operating
Range
-50
-60
-70
-80
-90
-800 -600 -400 -200
0
200 400 600 800
CP OFFSET CURRENT (uA)
Figure 17. Modelled vs. Measured Phase
Noise, Integer Mode HiK at 8 GHz [7]
-80
-100
Total Noise Simulated Using
Hittite PLL Design Software
Modelled PLL Floor
-120
-140
Measured Total Noise
-180
102 103 104 105 106 107 108
OFFSET (Hz)
Figure 16. RF Input Limits [6]
30
20
10
0 No Divider
Divide By 2
-10 RECOMMENDED OPERATING RANGE
-20
-30
-40
0
2000
4000
6000
8000
10000
RF INPUT FREQUENCY AT PRESCALAR (MHz)
Figure 18. Modelled vs. Measured Phase
Noise, Fractional Mode B, HiK at ~ 8 GHz [8]
-80
-100
Total Noise Simulated Using
Hittite PLL Design Software
Modelled PLL Floor
-120
-140
Measured Total Noise
-160
INTEGRATED RMS JITTER = 36.1 fs
100 Hz to 100 MHz
-160
INTEGRATED RMS JITTER = 44.2 fs
100 Hz to 100 MHz
-180
-180
102 103 104 105 106 107 108
102 103 104 105 106 107 108
OFFSET (Hz)
OFFSET (Hz)
[3] Output frequency = 8 GHz + 200 kHz using HMC508LP5E VCO, Reference Input = 100 MHz, PD frequency = 100 MHz, CP current = 2.5 mA,
Fractional Mode B, 20 kHz bandwidth Loop Filter. Spur at 200kHz due to RF signal at 8GHz + 200kHz, spur at 100kHz due to prescaler input at
4GHz+100kHz. Reference feedthrough spur at 100 MHz offset.
[4] Exact Frequency Mode channel spacing 100 kHz, Fractional N, Rfout = 8013.6 MHz using HMC508LP5E VCO, Reference Input = 100 MHz, PD
frequency = 100 MHz, Prescaler divide-by-2 selected. 20 kHz Loop Filter bandwidth, reference feedthrough spur at 100 MHz offset.
[5] Tuned to 8 GHz + 20 kHz, Prescaler at 4 GHz + 10 kHz, Loop bandwidth >> 20 kHz, Reference Frequency 50 MHz. Offset polarity should be
positive for inverting configurations and negative otherwise.
[6] Low frequency minimum power levels not characterized. Low frequency limitation is only a function of external AC coupling capacitance signal
slew rate.
[7] HiK integer mode measured at 8 GHz, Prescalar at 4 GHz, 50 MHz reference frequency.
[8] Active Fractional B Mode (Prescalar @ 4 GHz + 2.5 kHz), Reference Frequency 50 MHz.
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HMC703LP4E

8 GHz fractional synthesizer

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