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부품번호 AD9278 기능
기능 Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator
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AD9278 데이터시트, 핀배열, 회로
Data Sheet
Octal LNA/VGA/AAF/ADC
and CW I/Q Demodulator
AD9278
FEATURES
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low power: 88 mW per channel, TGC mode, 40 MSPS;
32 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 1.3 nV/Hz, max gain
Flexible power-down modes
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns
Low noise preamplifier (LNA)
Input-referred noise: 1.25 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/
750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >50 MHz
Variable gain amplifier (VGA)
Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
SNR: 70 dB, 12 bits up to 65 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel: >158 dBc/√Hz
Output-referred SNR: 153 dBc/√Hz, 1 kHz offset, −3 dBFS
GENERAL DESCRIPTION
The AD9278 is designed for low cost, low power, small size,
and ease of use for medical ultrasound and automotive radar. It
contains eight channels of a variable gain amplifier (VGA) with
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation.
Each channel features a variable gain range of 45 dB, a fully
differential signal path, an active input preamplifier termination,
and a maximum gain of up to 51 dB. The channel is optimized
for high dynamic performance and low power in applications
where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
and a 21.3 dB LNA gain, the LNA input SNR is roughly 88 dB.
In CW Doppler mode, each LNA output drives an I/Q demod-
ulator that has independently programmable phase rotation
with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
several features designed to maximize flexibility and minimize
system cost, such as a programmable clock, data alignment, and
programmable digital test pattern generation. The digital test
patterns include built-in fixed patterns, built-in pseudo random
patterns, and custom user-defined test patterns entered via the
serial port interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 PDWN STBY
DRVDD
LO-A TO LO-H
LOSW-A TO LOSW-H
LI-A TO LI-H
LG-A TO LG-H
LNA
I/Q
DEMODULATOR
VGA
AAF
8 CHANNELS
12-BIT
ADC
SERIAL
LVDS
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
LO
GENERATION
REFERENCE
SERIAL
PORT
INTERFACE
DATA
RATE
MULTIPLIER
FCO+
FCO–
DCO+
DCO–
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.




AD9278 pdf, 반도체, 판매, 대치품
Data Sheet
AD9278
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (−40°C to +85°C), fIN = 5 MHz,
RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.3 dB, LNA bias = default, PGA gain = 24 dB, GAIN− = 0.8 V, GAIN+ = 0 V, AAF LPF
cutoff = fSAMPLE/3 (MODE I/II/III), AAF LPF cutoff = fSAMPLE/4.5 (MODE IV), HPF cutoff = LPF cutoff/12, MODE I = fSAMPLE = 40 MSPS,
MODE II = fSAMPLE = 25 MSPS, MODE III = fSAMPLE = 50 MSPS, MODE IV = fSAMPLE = 65 MSPS, low power LVDS mode, unless otherwise
noted.
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
0.1 dB Input Compression Point
1 dB Input Compression Point
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Test Conditions/Comments
Single-ended input to differential
output
Single-ended input to single-ended
output
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
Min
Typ Max
15.6/17.9/21.3
9.6/11.9/15.3
1.00
0.75
0.45
1.20
0.90
0.60
2.2
Unit
dB
dB
V p-p
V p-p
V p-p
V p-p
V p-p
V p-p
V
V
Output Common Mode (LOSW-x)
Input Resistance (LI-x)
Input Capacitance (LI-x)
−3 dB Bandwidth
Input Noise Voltage
Input Noise Current
Noise Figure
Active Termination Matched
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Cutoff
In Range AAF Bandwidth
Tolerance
Group Delay Variation
Switch off
Switch on
RFB = 350 Ω, LNA gain = 21.3 dB
RFB = 1400 Ω, LNA gain = 21.3 dB
RFB = ∞, LNA gain = 21.3 dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RFB = ∞
RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
−3 dB, programmable
f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V
8
High-Z
1.5
50
200
15
22
100
80
50
1.60
1.42
1.27
1.5
7.8
6.7
5.6
6.1
5.3
4.7
±10
±0.3
18
Ω
V
kΩ
pF
MHz
MHz
MHz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
dB
dB
dB
dB
dB
dB
MHz
%
ns
Rev. A | Page 3 of 44

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AD9278 전자부품, 판매, 대치품
AD9278
Data Sheet
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 2.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
CW 4LO INPUTS (4LO+, 4LO−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK, RESET)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
Input Resistance
Input Capacitance
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (IOL = 50 μA)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Min
250
250
1.2
1.2
1.2
0
247
1.125
Typ Max
CMOS/LVDS/LVPECL
1.2
20
1.5
CMOS/LVDS/LVPECL
1.2
20
1.5
3.6
0.3
30
0.5
3.6
0.3
70
0.5
DRVDD + 0.3
0.3
30
2
LVDS
Offset binary
454
1.375
LVDS
Full 150
250
Full 1.10
1.30
Offset binary
Full 0.05
Unit
mV p-p
V
kΩ
pF
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. A | Page 6 of 44

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