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PDF NJW4372 Data sheet ( Hoja de datos )
| Número de pieza | NJW4372 | |
| Descripción | PULSE INPUT STEPPER MOTOR DRIVER | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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NJW4372
PULSE INPUT STEPPER MOTOR DRIVER
■ GENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW4372 is a high efficiency bipolar drive stepper motor
driver IC, which controls steps and direction by simple input pulse
train. DMOS H bridge outputs realize high efficiency, low heat
motor application. The control circuit is optimized for logic power
supplies and interfaces. Therefore it corresponds to plural kind of
logic voltages such as 5.0V and 3.3V.
The NJW4372 has PWM constant current circuits, a Torque
Select function, an Enable function and a Brake function. These
NJW4372V
easy and convenient functions make NJW4372 suitable for various
applications.
■ FEATURES
Logic Supply Voltage
Motor Supply Voltage
Output Current
VDD=2.7V to 5.5V
VMM=9V to 36V
Io=500mA typ.
Low ON Resistance Output RO(H+L) = 0.8Ω typ.
Low Quiescent Current
IDD=0.75mA typ. / IMM=1.65mA typ.
STEP&DIR (pulse train) Input Control
TTL Compatible Input
Constant Current Control
Maximum Current Select (Torque Select) Function
Step Mode (Full / Half step) Select, ENABLE, RESET Function
BRAKE (High side outputs turn on) Function
MO, ALARM Output Function
Protection Circuit
OCP, UVLO, TSD
BCD Technology
Package
SSOP32
■ BLOCK DIAGRAM
RESET
STEP
DIR
HSM
MO
VR
TOR1
TOR2
ENABLE
BRAKE
GND
VDD
BIAS
POR UVLO_VDD
VMM
UVLO_VMM
SENSE1
OSC
OCP
VMM
OCP
PROTECTION
OCP TSD
RESET
POR
OUT1B
OUT1A
OUT2A
OUT2B
SENSE2
ALARM
Ver.2017-01-17
-1-
1 page  
NJW4372
■ ELECTRICAL CHARACTERISTICS
(VMM=24V, VDD/VIN=5.0V, TOR1/TOR2=0V, RMO=5kΩ, RALARM=5kΩ, Ta=25 C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
■ CONSTANT CURRENT DETECTION BLOCK
Detection Voltage 1
(100% Current Level)
VTOR1
TOR1=L, TOR2=L
VR=3.3V
460 500 540 mV
290 330 370 mV
Detection Voltage 2
(70% Current Level)
VTOR2
TOR1=H, TOR2=L
VR=3.3V
310 350 390 mV
191 231 271 mV
Detection Voltage 3
(40% Current Level)
VTOR3
TOR1=L, TOR2=H
VR=3.3V
160 200 240 mV
92 132 172 mV
Detection Voltage 4
(20% Current Level)
VTOR4
TOR1=H, TOR2=H
VR=3.3V
60 100 140 mV
26 66 106 mV
■ THERMAL SHUTDOWN BLOCK
TSD Operating Temperature
TTSD1
TSD Recovery Temperature
TTSD2
TSD Hysteresis Temperature
∆TTSD
■ UNDER VOLTAGE LOCK OUT BLOCK 1 (LOGIC BLOCK)
- 170 -
- 140 -
- 30 -
C
C
C
UVLO Operating Voltage
VUVLO1
UVLO Recovery Voltage
VUVLO2
UVLO Hysteresis Voltage
∆VUVLO
■ UNDER VOLTAGE LOCK OUT BLOCK 2 (MOTOR BLOCK)
1.7 2.0 2.3
1.85 2.15 2.45
0.05 0.15
0.3
V
V
V
UVLO Operating Voltage
VUVLO1
6.5 7.0 7.5
V
UVLO Recovery Voltage
VUVLO2
6.8 7.3 7.8
V
UVLO Hysteresis Voltage
∆VUVLO
0.2 0.3 0.4
V
■ THERMAL RESISTANCE CHARACTERISTICS
PARAMETER
Junction - Ambient Thermal
Resistance 1
Junction - Case Surface
Thermal Resistance 1
Junction - Ambient Thermal
Resistance 2
SYMBOL
ja_1
Ψjt_1
ja_2
TEST CONDITIONS
Mounted on glass epoxy board based on EIA/JEDEC.
(114.3 76.2 1.6mm, FR-4, 2Layers)
Mounted on glass epoxy board based on EIA/JEDEC.
(114.3 76.2 1.6mm, FR-4, 2Layers)
Mounted on glass epoxy board based on EIA/JEDEC.
(114.3 76.2 1.6mm, FR-4, 4Layers,
Inner Cu area : 74.2 74.2mm)
MIN.
-
-
-
TYP.
-
17
-
MAX.
110
UNIT
C/W
- C/W
70 C/W
Junction - Case Surface
Thermal Resistance 2
Mounted on glass epoxy board based on EIA/JEDEC.
Ψjt_2 (114.3 76.2 1.6mm, FR-4, 4Layers,
Inner Cu area : 74.2 74.2mm)
-
8
- C/W
■ POWER DISSIPATION vs. AMBIENT TEMPERATURE
2000
NJW4372V PD vs. Ta
(Topr=-40 to +85°C,Tj=150°C)
1800
1600
1400
Mounted on 4-Layer Board
(FR4 114.3×76.2×1.6mm)
Internal Cu area:74.2x74.2mm
1200
1000
800
Mounted on 2-Layer Board
(FR4 114.3×76.2×1.6mm)
600
400
200
0
-50 -25
0 25 50
Ambient Temperature Ta(°C)
75
928mW
590mW
100
125
Ver.2017-01-17
-5-
5 Page 
NJW4372
■ TIMING CHART
TOR1=TOR2=L(100%), Current Direction : I1+=OUT1A→OUT1B, I2+=OUT2A→OUT2B
VDD
RESET
ENABLE
DIR
HSM
BRAKE
STEP
Pos 0 2 4 6 0 1 2 3 4 5 6 7 0 6 4 2 0 7 6 5 4 3 2 1 0 2
+
0
24666602
I1
-
+
I2
-
RESET
MO
VDD ON FULL CW
HALF CW
FULL CCW
HALF CCW
ENABLE
BRAKE
▪ During Power ON sequence, set RESET, ENABLE and STEP pins to “L” level for preventing malfunction.
▪ When RESET pin is “L” level, motor outputs are turned off and Translator is initialized.
During this period, Translator can’t accept STEP signal.
▪ When ENABLE pin is “L” level, motor outputs are turned off but Translator isn’t initialized.
During this period, Translator can accept STEP signal. When STEP signal is received, Translator operates sequence.
▪ When BRAKE pin is “H” level, all high side FETs are turned on and the breaking current flows through motor winding.
During this period, Translator can’t accept STEP signal.
▪ The priority of function is as follows: RESET > ENABLE > BRAKE.
■ OCP FUNCTION TIMING CHART
After RESET/POR
Accumulation Count Period
RESET/POR Command
After RESET/POR
OCP Detection Current
Io
VOUT
1st time
2nd time
3rd time 4th time
tocp
ON
tb+tocp
OFF(Hi-Z)
5th time
Stop Retention
Output ON/OFF Condition
(Phase, ENABLE, BRAKE,
PWM, UVLO, TSD)
ON
OFF
VALARM
ALARM ON
Local OSC
Release Command
tocp : OCP Delay Time
tb : Blanking Time
▪ The OCP circuit counts the OCP detection during the period of RESET or POR (Power-on).
When OCP circuit detects five times, OUT pins turn off and retain, then ALARM pin outputs ALARM signal.
After first OCP detection, the motor outputs are turned off temporarily.
However, motor outputs restart by trigger of internal Local OSC until five times.
▪ Detection count, latch-off status and ALARM output can release by the following way.
(1) Restart logic power supply (Power on Reset) (2) Input RESET signal
▪ The interval time between OCP detection and turning off is depend on output status.
When ON state, the interval time is OCP Delay Time "tocp".
Otherwise the interval time adds tocp and Blanking Time "tb".
Ver.2017-01-17
- 11 -
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NJW4372.PDF ] | |
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