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ADP5586 데이터시트 PDF




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부품번호 ADP5586 기능
기능 Keypad Decoder and I/O Port Expander
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ADP5586 데이터시트, 핀배열, 회로
Data Sheet
Keypad Decoder and I/O Port Expander
ADP5586
FEATURES
16-element FIFO for event recording
10 configurable I/Os allowing for such functions as
Keypad decoding for a matrix of up to 5 × 5
Key press/release interrupts
GPIO functions
GPI with selectable interrupt level
100 kΩ or 300 kΩ pull-up resistors
300 kΩ pull-down resistors
GPO with push-pull or open drain
Programmable logic block
Pulse generators
Periods and on times
Above 30 sec in 125 ms increments
Up to 255 ms in 1 ms increments
Reset generator
I2C interface with Fast-mode Plus (Fm+) support of up to 1 MHz
Open-drain interrupt output
16-ball WLCSP, 1.59 mm × 1.59 mm
APPLICATIONS
Keypad entries and input/output expansion capabilities
Smartphones, remote controls, and cameras
Healthcare, industrial, and instrumentation
GENERAL DESCRIPTION
The ADP5586 is a 10-input/output port expander with a built-in
keypad matrix decoder, programmable logic, reset generator, and
pulse generators. Input/output expander ICs are used in portable
devices (phones, remote controls, and cameras) and nonportable
applications (healthcare, industrial, and instrumentation). I/O
expanders can be used to increase the number of I/Os available
to a processor or to reduce the number of I/Os required through
interface connectors for front panel designs.
The ADP5586 handles all key scanning and decoding and can
flag the main processor, via an interrupt line, that new key events
have occurred. GPI changes and logic changes can also be tracked
RST/R5
SDA
SCL
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
ADP5586
UVLO
POR
OSCILLATOR
I2C INTERFACE
R0
R1
R2
R3
R4 I/O
CONFIG
C0
C1
C2
C3
C4
KEY SCAN
AND
DECODE
GPI SCAN
AND
DECODE
LOGIC
PULSE
GEN 1
PULSE
GEN 2
RESET
GEN
Figure 1.
REGISTERS
INT
as events via the FIFO, eliminating the need to monitor different
registers for event changes. The ADP5586 is equipped with a
FIFO to store up to 16 events. Events can be read back by the
processor via an I2C-compatible interface.
The ADP5586 eliminates the need for the main processor to
monitor the keypad, thus reducing power consumption and/or
increasing processor bandwidth for performing other functions.
The programmable logic functions allow common logic require-
ments to be integrated as part of the GPIO expander, thus saving
board area and cost.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADP5586 pdf, 반도체, 판매, 대치품
Data Sheet
ADP5586
SPECIFICATIONS
VDD = 1.8 V to 3.3 V, TA = TJ = −40°C to +85°C, unless otherwise noted.1
Table 1.
Parameter
SUPPLY VOLTAGE
VDD Input Voltage Range
Undervoltage Lockout Threshold
SUPPLY CURRENT
Standby Current
Operating Current (One Key Press)
PULL-UP, PULL-DOWN RESISTANCE
Pull-Up
Option 1
Option 2
Pull-Down
INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1,
R2, R3, R4, R5, C0, C1, C2, C3, C4)
Input Voltage
Logic Low
Logic High
Input Leakage Current (Per Pin)
PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1,
R2, R3, R4, R5, C0, C1, C2, C3, C4
Output Voltage
Logic Low
Logic High
Logic High Output Leakage Current
(Per Pin)
OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA)
Output Voltage
Logic Low
INT
SDA
Logic High Output Leakage Current
(Per Pin)
Logic Propagation Delay
Flip-Flop (FF) Hold Time2
FF Setup Time2
GPIO Debounce2
Internal Oscillator Frequency3
Symbol Test Conditions/Comments
Min
VDD
UVLOVDD
UVLO active, VDD falling
UVLO inactive, VDD rising
1.65
1.2
ISTNBY
ISCAN1
ISCAN2
VDD = 1.65 V
VDD = 3.3 V
Scan = 10 ms, CORE_FREQ = 50 kHz,
scan active, 300 kΩ pull-up, VDD = 1.65 V
Scan = 10 ms, CORE_FREQ = 50 kHz,
scan active, 300 kΩ pull-up, VDD = 3.3 V
50
150
150
Typ
1.3
1.4
1
1
30
75
100
300
300
VIL
VIH
VI-LEAK
0.7 × VDD
0.1
VOL1
VOL2
VOH
VOH-LEAK
Sink current = 10 mA, maximum of five
GPIOs active simultaneously
Sink current = 10 mA, all GPIOs active
simultaneously
Source current = 5 mA
0.7 × VDD
0.1
VOL3
VOL4
VOH-LEAK
ISINK = 10 mA
ISINK = 20 mA
OSCFREQ
0.1
125
0
175
720 800
Max
3.6
1.6
4
10
40
85
150
450
450
0.3 × VDD
1
0.4
0.5
1
0.4
0.4
1
300
70
880
1 All limits at temperature extremes are guaranteed via correlation, using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V.
2 Guaranteed by design.
3 All timers are referenced from the base oscillator and have the same ±10% accuracy.
Unit
V
V
V
μA
µA
µA
μA
kΩ
kΩ
kΩ
V
V
µA
V
V
V
µA
V
V
µA
ns
ns
ns
µs
kHz
Rev. 0 | Page 3 of 44

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ADP5586 전자부품, 판매, 대치품
ADP5586
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
12 34
A
VDD SDA SCL GND
B
R0 INT RST/R5 C0
C
R2 R1 C1 C2
D
R4 R3 C3 C4
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No. Mnemonic Description
A1 VDD
Supply Voltage Input.
A2 SDA
I2C Data Input/Output.
A3 SCL
I2C Clock Input.
A4 GND
Ground.
B1 R0
GPIO 1 (GPIO Alternate Function: Logic Block Output LY). This pin functions as Row 0 when configured in keypad mode.
B2 INT
Open-Drain Interrupt Output.
B3 RST/R5
Input Reset Signal (RST). The reset signal function applies to all models except the ADP5586ACBZ-01-R7.
GPIO 6/Row 5 (R5). This function applies only to the ADP5586ACBZ-01-R7 model.
B4 C0
GPIO 7 (GPIO Alternate Function: PULSE_GEN_1). This pin functions as Column 0 when configured in keypad mode.
C1 R2
GPIO 3 (GPIO Alternate Function: Logic Block Input LB). This pin functions as Row 2 when configured in keypad mode.
C2 R1
GPIO 2 (GPIO Alternate Function: Logic Block Input LA). This pin functions as Row 1 when configured in keypad mode.
C3 C1
GPIO 8 (GPIO Alternate Function: PULSE_GEN_2). This pin functions as Column 1 when configured in keypad mode.
C4 C2
GPIO 9. This pin functions as Column 2 when configured in keypad mode.
D1 R4
GPIO 5 (GPIO Alternate Function: RESET_OUT). This pin functions as Row 4 when configured in keypad mode.
D2 R3
GPIO 4 (GPIO Alternate Function: Logic Block Input LC). This pin functions as Row 3 when configured in keypad mode.
D3 C3
GPIO 10. This pin functions as Column 3 when configured in keypad mode.
D4 C4
GPIO 11. This pin functions as Column 4 when configured in keypad mode.
Rev. 0 | Page 6 of 44

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