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ADPD107 데이터시트 PDF




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부품번호 ADPD107 기능
기능 Photometric Front Ends
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ADPD107 데이터시트, 핀배열, 회로
Data Sheet
FEATURES
Multifunction photometric front end
Fully integrated AFE, ADC, LED drivers, and timing core
Enables best-in-class ambient light rejection capability
without the need for photodiode optical filters
Three 370 mA LED drivers
Flexible, multiple, short LED pulses per optical sample
20-bit burst accumulator enabling 20 bits per sample period
On-board sample to sample accumulator, enabling up to
27 bits per data read
Low power operation
SPI, I2C interface, and 1.8 V analog/digital core
Flexible sampling frequency ranging from 0.122 Hz to 3820 Hz
FIFO data operation
APPLICATIONS
Wearable health and fitness monitors
Clinical measurements, for example, SpO2
Industrial monitoring
Background light measurements
Photometric Front Ends
ADPD105/ADPD106/ADPD107
GENERAL DESCRIPTION
The ADPD105/ADPD106/ADPD107 are highly efficient,
photometric front ends, each with an integrated 14-bit analog-
to-digital converter (ADC) and a 20-bit burst accumulator that
works with flexible light emitting diode (LED) drivers. The
accumulator is designed to stimulate an LED and measure
the corresponding optical return signal. The data output and
functional configuration occur over a 1.8 V I2C interface on the
ADPD105 or SPI on the ADPD106 and ADPD107. The control
circuitry includes flexible LED signaling and synchronous
detection.
The analog front end (AFE) features best-in-class rejection of signal
offset and corruption due to modulated interference commonly
caused by ambient light.
Couple the ADPD105/ADPD106/ADPD107 with a low
capacitance photodiode of <100 pF for optimal performance.
The ADPD105/ADPD106/ADPD107 can be used with any LED.
The ADPD105 is available in a 2.46 mm × 1.4 mm WLCSP and a
4 mm × 4 mm LFCSP. The SPI only versions, ADPD106 and
ADPD107, are available in a 2.46 mm × 1.4 mm WLCSP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADPD107 pdf, 반도체, 판매, 대치품
ADPD105/ADPD106/ADPD107
FUNCTIONAL BLOCK DIAGRAMS
PDC
PD1-2
TIME SLOT
SWITCH
PD3-4
PD3-4 ON
ADPD105/
ADPD107
ONLY
ANALOG BLOCK
AFE:
SIGNAL CONDITIONING
TIA
VBIAS
BPF
±1 INTEGRATOR
TIA
VBIAS
AFE:
SIGNAL CONDITIONING
BPF
±1 INTEGRATOR
TIA
VBIAS
TIA
VBIAS
AFE:
SIGNAL CONDITIONING
BPF
±1 INTEGRATOR
AFE:
SIGNAL CONDITIONING
BPF
±1 INTEGRATOR
AVDD
DVDD
ADPD105/
ADPD106/
ADPD107
WLCSP VERSIONS
14-BIT
ADC
AFE
CONFIGURATION
A
B
SLOT
SELECT
TIME SLOT A
DATA
TIME SLOT B
DATA
DIGITAL
DATAPATH
AND
INTERFACE
CONTROL
LED3
LED2
LED1
LEDX3
LEDX2
LEDX1
VLED
LGND
LED3 DRIVER
LED2 DRIVER
LED1 DRIVER
LED3 LEVEL AND TIMING CONTROL
LED2 LEVEL AND TIMING CONTROL
LED1 LEVEL AND TIMING CONTROL
Figure 1. Block Diagram for ADPD105/ADPD106/ADPD107 WLCSP (Chip Scale Package) Versions
Data Sheet
VREF
1µF
GPIO0
GPIO1
MOSI
MISO
SCLK
CS
ADPD106/
ADPD107
ONLY
SDA
SCL
ADPD105
ONLY
DGND
AGND
Rev. A | Page 4 of 66

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ADPD107 전자부품, 판매, 대치품
Data Sheet
ADPD105/ADPD106/ADPD107
PERFORMANCE SPECIFICATIONS
AVDD = DVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted.
Table 3.
Parameter
DATA ACQUISITION
Resolution
Resolution/Sample
Resolution/Data Read
LED DRIVER
LED Current Slew Rate1
Rise
Fall
LED Peak Current
Driver Compliance Voltage
LED PERIOD
Sampling Frequency3
CATHODE PIN (PDC) VOLTAGE
During All Sampling Periods
During Slot A Sampling
During Slot B Sampling
During Sleep Periods
PHOTODIODE INPUT PINS/
ANODE VOLTAGE
During All Sampling Periods
During Sleep Periods
Test Conditions/Comments
Single pulse
64 to 255 pulses
64 to 255 pulses and sample average = 128
Slew rate control setting = 0; TA = 25°C; ILED = 70 mA
Slew rate control setting = 7; TA = 25°C; ILED = 70 mA
Slew rate control setting = 0, 1, 2; TA = 25°C; ILED = 70 mA
Slew rate control setting = 6, 7; TA = 25°C; ILED = 70 mA
LED pulse enabled
Voltage above ground required for LED driver operation
AFE width = 4 μs2
AFE width = 3 μs
Time Slot A only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Time Slot B only; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Both time slots; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Time Slot A only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Time Slot B only; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Both time slots; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 μs; SLOTA_
LED_PERIOD = 19 μs
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 14
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x04
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x35
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x04
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x35
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1
Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2
Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3
Min Typ Max Unit
14 Bits
20 Bits
27 Bits
0.122
240
1400
3200
4500
0.6
19
17
370
3230
mA/μs
mA/μs
mA/μs
mA/μs
mA
V
μs
μs
Hz
0.122
3820 Hz
0.122
1750 Hz
0.122
2257 Hz
0.122
2531 Hz
0.122
1193 Hz
1.8 V
1.3 V
1.8 V
1.3 V
1.55 V
0V
1.8 V
1.3 V
1.55 V
0V
1.8 V
1.3 V
1.8 V
1.3 V
1.55 V
0V
1.3
Cathode voltage
V
V
1 LED inductance is negligible for these values. The effective slew rate slows with increased inductance.
2 Minimum LED period = (2 × AFE width) + 5 μs.
3 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the output data rate.
4 This mode may induce additional noise and is not recommended unless absolutely necessary. The 1.8 V setting uses VDD, which contains greater amounts of
differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance
of the photodiode of the magnitude of C × dV/dt.
5 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode.
Rev. A | Page 7 of 66

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