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부품번호 ADV7281 기능
기능 4x Oversampled SDTV Video Decoder
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ADV7281 데이터시트, 핀배열, 회로
Data Sheet
10-Bit, 4× Oversampled SDTV Video
Decoder with Differential Inputs
ADV7281
FEATURES
Worldwide NTSC/PAL/SECAM color demodulation support
One 10-bit analog-to-digital converter (ADC), 4× oversampling
per channel for CVBS, Y/C, and YPrPb modes
Analog video input channels with on-chip antialiasing filter
ADV7281: up to 4 input channels
ADV7281-M: up to 6 input channels
ADV7281-MA: up to 8 input channels
Video input support for CVBS (composite), Y/C (S-Video),
and YPrPb (component)
Fully differential, pseudo differential, and single-ended
CVBS video input support
NTSC/PAL/SECAM autodetection
Short-to-battery (STB) diagnostics on 2 video inputs
(ADV7281 and ADV7281-M only)
Up to 4 V common-mode input range solution
Excellent common-mode noise rejection capabilities
5-line adaptive 2D comb filter and CTI video enhancement
Adaptive Digital Line Length Tracking (ADLLT), signal
processing, and enhanced FIFO management provide
mini-time base correction (TBC) functionality
Integrated automatic gain control (AGC) with adaptive
peak white mode
Fast switching capability
Adaptive contrast enhancement (ACE)
Down dither (8-bit to 6-bit)
Rovi (Macrovision) copy protection detection
MIPI CSI-2 output interface (ADV7281-M and ADV7281-MA)
8-bit ITU-R BT.656 YCrCb 4:2:2 output (ADV7281)
Full featured vertical blanking interval (VBI) data slicer
Power-down mode available
2-wire, I2C-compatible serial interface
Qualified for automotive applications
−40°C to +105°C temperature grade
32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP
APPLICATIONS
Smartphone/multimedia handsets
Automotive infotainment
DVRs for video security
Media players
GENERAL DESCRIPTION
The ADV7281/ADV7281-M/ADV7281-MA are versatile
one-chip, multiformat video decoders. The ADV7281/
ADV7281-M/ADV7281-MA automatically detect standard
analog baseband video signals compatible with worldwide
NTSC, PAL, and SECAM standards in the form of composite,
S-Video, and component video.
The ADV7281 converts the analog video signals into a YCrCb
4:2:2 video data stream that is compatible with the 8-bit ITU-R
BT.656 interface standard.
The ADV7281-M/ADV7281-MA convert the analog video
signals into an 8-bit YCrCb 4:2:2 video data stream that is
output over a mobile industry processor interface (MIPI®)
CSI-2 interface.
The analog video inputs of the ADV7281/ADV7281-M/
ADV7281-MA accept single-ended, pseudo differential, and
fully differential signals. The ADV7281 provides four analog
inputs and two STB diagnostic pins. The ADV7281-M provides
six analog inputs, two STB diagnostic pins, and three general-
purpose outputs. The ADV7281-MA provides eight analog
inputs and three general-purpose outputs.
The ADV7281/ADV7281-M/ADV7281-MA are programmed
via a 2-wire, serial bidirectional port (I2C compatible) and
are fabricated in a 1.8 V CMOS process. The ADV7281/
ADV7281-M/ADV7281-MA are provided in space-saving
LFCSP surface-mount, RoHS-compliant packages. The
ADV7281/ADV7281-M/ADV7281-MA are rated over the
−40°C to +105°C temperature range. This makes the ADV7281/
ADV7281-M/ADV7281-MA ideal for automotive applications.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADV7281 pdf, 반도체, 판매, 대치품
Data Sheet
FUNCTIONAL BLOCK DIAGRAMS
ADV7281
XTALP
XTALN
ADV7281
CLOCK PROCESSING BLOCK
PLL ADLLT PROCESSING
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
AIN3
AIN4
AA
FILTER
AA
FILTER
AA
FILTER
AA
FILTER
10-BIT ADC
+
SHA
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
VBI SLICER
COLOR
DEMOD
DIAGNOSTICS
REFERENCE
I2C/CONTROL
LCC
ACE
DOWN
DITHER
8-BIT
PIXEL DATA
P0 TO P7
INTRQ
DIAG1 DIAG2
SCLK SDATA ALSB RESET PWRDWN
Figure 1. ADV7281 Functional Block Diagram
XTALP
XTALN
ADV7281-M
CLOCK PROCESSING BLOCK
PLL ADLLT PROCESSING
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AA
FILTER
AA
FILTER
AA
FILTER
AA
FILTER
10-BIT ADC
+
SHA
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
VBI SLICER
COLOR
DEMOD
DIAGNOSTICS
REFERENCE
I2C/CONTROL
MIPI
Tx
CLKP
CLKN
D0P
D0N
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
INTRQ
DIAG1 DIAG2
SCLK SDATA ALSB RESET PWRDWN
Figure 2. ADV7281-M Functional Block Diagram
XTALP
XTALN
ADV7281-MA
CLOCK PROCESSING BLOCK
PLL ADLLT PROCESSING
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AA
FILTER
AA
FILTER
AA
FILTER
AA
FILTER
10-BIT ADC
+
SHA
ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
VBI SLICER
COLOR
DEMOD
REFERENCE
I2C/CONTROL
MIPI
Tx
CLKP
CLKN
D0P
D0N
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
INTRQ
SCLK SDATA ALSB RESET PWRDWN
Figure 3. ADV7281-MA Functional Block Diagram
Rev. B | Page 3 of 32

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ADV7281 전자부품, 판매, 대치품
ADV7281
Data Sheet
ANALOG SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 3.
Parameter
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions/Comments Min Typ Max Unit
Clamps switched off
0.1 μF
10 MΩ
0.4 mA
0.4 mA
10 μA
10 μA
CLOCK AND I2C TIMING SPECIFICATIONS
AVDD, DVDD, PVDD, and MVDD = 1.71 V to 1.89 V, DVDDIO = 2.97 V to 3.63 V, specified at operating temperature range, unless otherwise noted.
Specifications guaranteed by characterization. Note that MVDD only applies to the ADV7281-M/ADV7281-MA.
Table 4.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Times
SCLK and SDATA Fall Times
Setup Time (Stop Condition)
RESET INPUT
RESET Pulse Width
Symbol Min
t1 0.6
t2 1.3
t3 0.6
t4 0.6
t5 100
t6
t7
t8
5
Typ Max
28.63636
±50
400
300
300
0.6
Unit
MHz
ppm
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
SDATA
SCLK
t3 t5
t3
t6
t2
t1
t7
Figure 4. I2C Timing Diagram
t4
t8
Rev. B | Page 6 of 32

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