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PDF NJU6541B Data sheet ( Hoja de datos )
| Número de pieza | NJU6541B | |
| Descripción | Static 1/2 1/3 1/4 Duty LCD Driver | |
| Fabricantes | New Japan Radio | |
| Logotipo |  |
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Preliminary NJU6541B
Static 1/2 1/3 1/4 Duty LCD Driver
GENERAL DESCRIPTION
The NJU6541B is a Static or 1/2,1/3,1/4 duty segment
type LCD driver. It incorporates 4 common driver circuits
and 120 segment driver circuits. The NJU6541B can
drive maximum 480 segments in 1/4 duty ratio, and can
use 3-Wire serial I/F.
In addition, the NJU6541B's useful functions meet a
wide range of applications.
PACKAGE OUTLINE
FEATURES
NJU6541B
LCD driving circuit
:Max. 120outputs (4 outputs as for general purpose ports)
Programmable Duty Ratio
Static
:Driving max. 120 segments
1/2 Duty Ratio
:Driving max. 240 segments
1/3 Duty Ratio
:Driving max. 360 segments
1/4 Duty Ratio
:Driving max. 480 segments
General Purpose Port :Driving max 4outputs (SEG1-SEG4:4outputs as for general purpose ports)
Key Scan Function
:Max 30Key(5-out x 6-in matrix)
Programmable Bias Ratio
:1/2, 1/3 bias ratio (Static:1/1)
Serial Data Transfer :Shift clock max. 2MHz
Oscillator
:CR oscillation with external resistor and capacitance, or external oscillation
signal input
Operating Wave Form :A wave form, B wave form
Electrical Variable Resistance :8-steps
Power ON Initialize Circuit On-Chip
Useful Instruction Set :Duty select, Bias select, Wave form select, Oscillation select, Segment or general
purpose ports select, Segment or Key scan output select, E.V.R select,
Display ON/OFF, Key scan ON/OFF
Operating Voltage
:3.0V / 5.0V
C-MOS Technology :P-Sub
Package Outline
:LQFP144 20mm*20mm t=1.7mm(max) Pin-pitch=0.5mm
BLOCK DIAGRAM
VDD
V0
V1
EVR
REQ S5 K1- K6 COM1
COM4
Key Scan
Common
Driver
SEG1/P1 SEG4/P4 SEG5 SEG115 SEG117/S1 SEG120/S4
Segment Driver
V2
Latch
V3
VSS
OSC
SIO
CSb
SCL
RSTB
TEST
OSC
Serial I/F
Display Reg
Decoder
Command Reg
Power ON Reset
Ver.2013-04-19
-1-
1 page  
Preliminary NJU6541B
(2) Serial Data transfer
The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. During
CS=“L”, serial data is obtainable and will be read in at the rising edge of SCL signal.
After CSb becoming low, by the first word, address data is distinguished by D7 and D6.
In the case of address data(D7,D6=”0,1”), the 2nd data can be transferred continually and interrupted as
display data even if CSb maintained low. In this case, every 8-bits data will be confirmed as a word either by
the falling edge of the 8th SCL clock or by the rising edge of the CSb clock.
After CSb becoming low, if the first word is command data(D7,D6=”1,0” or “1,1”), the after data is invalid even
though transfer can be continued without changing the polarity of CSb.( Effective the first word)
At the falling edge of CSb, SCL can be either “H” or “L”, but, at the rising edge of CSb, SCL must be low.
At this rising edge, one word is confirmed data
CSb
SCL
SIO
CSb
SCL
D7 D6 D5 D4 D3 D2 D1 D0
Fig.1 Timing Serial Data Transfer
At this rising edge of CSb, when
SCL=”L”. one word is confirmed.
SIO
WORD 1
WORD 2
WORD n
Valid
In Valid
Fig.2 Serial Interface Format
Ver.2013-04-19
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5 Page 
Preliminary NJU6541B
(8) Command Register5
• Command Register 5 is used to read out of Key scan data. When the D7 to D4 bits of the 1st word are (1,1,0,0),
the D3 to D0 bit are recognized as command data 5.
The output key scan data is when the after input Key data read command. And then, Key scan read out is
change to “OFF” ( Write status ).
Command Register 5 Default value.
Read/Write
D7 D6 D5
110
: Key Scan data Red out OFF
D4 D3 D2 D1
0* * *
D0
*
Recognize data
REQ
CSb
SCL
SIO
Key Data
Read out Signal
Command
Register5
Key Data 1
Key Data
Read out ON
Key Data 5
Key Data
Read out OFF
Ver.2013-04-19
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NJU6541B.PDF ] | |
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