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PDF CY8C20637 Data sheet ( Hoja de datos )
| Número de pieza | CY8C20637 | |
| Descripción | 1.8V CapSense Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8C20xx7/S
1.8 V CapSense® Controller with
SmartSense™ Auto-tuning
31 Buttons, 6 Sliders, Proximity Sensors
1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors
Features
■ QuietZone™ Controller
❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™)
sensing algorithm for robust performance
❐ High Sensitivity (0.1 pF) and best-in-class SNR performance
to support:
• Overlay thickness of 15 mm for glass and 5 mm plastic
• Proximity Solutions
❐ Superior noise immunity performance against conducted and
radiated noise and ultra low radiated emissions
• Standardized user modules for overcoming noise
■ Low power CapSense® block with SmartSense Auto-tuning
❐ Low average power consumption –
• 28 µA/sensor in run time (wake-up and scan once every
125 ms)
❐ SmartSense_EMC_PLUS Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
■ Driven shield available on five GPIO pins
❐ Delivers best-in class water tolerant designs
❐ Robust proximity sensing in the presence of metal objects
❐ Supports longer trace lengths
❐ Max load of 100 pF (3 MHz)
■ Powerful Harvard-architecture processor
❐ M8C CPU with a max speed of 24 MHz
■ Operating Range: 1.71 V to 5.5 V
❐ Standby Mode 1.1 μA (Typ)
❐ Deep Sleep 0.1 μA (Typ)
■ Operating Temperature range: –40 oC to +85 oC
■ Flexible on-chip memory
❐ 8 KB flash, 1 KB SRAM
❐ 16 KB flash, 2 KB SRAM
❐ 32 KB flash, 2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Read while Write with EEPROM emulation
❐ In-system programming simplifies manufacturing process
■ 4 Clock Sources
❐ Internal main oscillator (IMO): 6/12/24 MHz
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ External 32 KHz Crystal Oscillator
❐ External Clock Input
■ Programmable pin configurations
❐ Up to 34 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO (Analog and Digital)
❐ High sink current of 25 mA per GPIO
• Max sink current 120 mA for all I/Os combined
❐ Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2, 3 and 4
❐ Configurable internal pull-up, high-Z and open drain modes
❐ Selectable, regulated digital I/O on port 1
❐ Configurable input threshold on port 1
■ Versatile Analog functions
❐ Internal analog bus supports connection of multiple sensors
to form ganged proximity sensor
❐ Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
■ Additional system resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Selectable Clock stretch or Forced Nack Mode
• I2C wake from sleep with Hardware address match
❐ 12 MHz (Configurable) SPI master and slave
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ 10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐ Two general-purpose high speed, low power analog
comparators
■ Complete development tools
❐ Free development tool (PSoC Designer™)
■ Sensor and Package options
❐ 10 Sensing Inputs – 16-pin QFN, 16-pin SOIC
❐ 16 Sensing Inputs – 24-pin QFN
❐ 24 Sensing Inputs – 30-pin WLCSP
❐ 25 Sensing Inputs – 32-pin QFN
❐ 31 Sensing Inputs – 48-pin QFN
Errata: For information on silicon errata, see “Errata” on page 37. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-69257 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 2, 2016
1 page  
CY8C20xx7/S
Additional System Resources
System resources provide additional capability, such as
configurable I2C slave, SPI master/slave communication
interface, three 16-bit programmable timers, various system
resets supported by the M8C low voltage detection and power-
on reset. The merits of each system resource are listed here:
■ The I2C slave/SPI master-slave module provides 50/100/
400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
■ The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■
The I2C enhanced slave interface
buffer to the external I2C master.
appears
Using a
as a 32-byte RAM
simple predefined
protocol, the master controls the read and write pointers into
the RAM. When this method is enabled, the slave does not stall
the bus when receiving data bytes in active mode. For more
details, refer to the I2CSBUF User Module datasheet.
■ Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power-
on reset (POR) circuit eliminates the need for a system
supervisor.
■ An internal reference provides an absolute reference for
capacitive sensing.
■ A register-controlled bypass mode allows the user to disable
the LDO regulator.
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the CY8C20x37/
47/67/S PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
Application Notes/Design Guides
Application notes and design guides are an excellent
introduction to the wide variety of possible PSoC designs. They
are located at www.cypress.com/gocapsense. Select
Application Notes under the Related Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, Digi-
Key, Farnell, Future Electronics, and Newark. See “Development
Kits” on page 31.
Training
Free PSoC and CapSense technical training (on demand,
webinars, and workshops) is available online at
www.cypress.com/training. The training covers a wide variety of
topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, create a technical support case
or call technical support at 1-800-541-4736.
Document Number: 001-69257 Rev. *O
Page 5 of 45
5 Page 
CY8C20xx7/S
32-pin QFN (25 Sensing Inputs)[25]
Table 5. Pin Definitions – CY8C20437, CY8C20447/S, CY8C20467/S [26]
Pin
No.
Type
Digital Analog
Name
Description
Figure 6. CY8C20437, CY8C20447/S, CY8C20467/S Device
1 IOH
I P0[1] Integrating input
2 I/O
I P2[5] Crystal output (XOut)
3 I/O
4 I/O
5 I/O
6 I/O
7 I/O
8 IOHR
9 IOHR
I P2[3] Crystal input (XIn)
I P2[1]
I P4[3]
I P3[3]
I P3[1]
I P1[7] I2C SCL, SPI SS
I P1[5] I2C SDA, SPI MISO
AI , P0[1]
AI, XOut,P2[5]
AI , XIn, P2[3]
AI, P2[1]
AI, P4[3]
AI, P3[3]
AI, P3[1]
AI , I 2C SCL, SPI SS,P1[7]
1
2
3
4
5
6
7
8
24 P2[4] , AI
23 P2[2] , AI
22 P2[0] , AI
QFN
(Top View)
21 P4[2] , AI
20 P4[0] , AI
19 P3[2] , AI
18 P3[0] , AI
17 XRES
10 IOHR
11 IOHR
I
I
12 Power
13 IOHR
I
P1[3]
P1[1]
VSS
P1[0]
SPI CLK.
ISSP CLK[27], I2C SCL, SPI
MOSI.
Ground connection[30]
SISPSIPCDLKA[T2A8][27], I2C SDA,
14 IOHR
I P1[2] Driven Shield Output (optional)
15 IOHR
I P1[4] Optional external clock input
(EXTCLK)
16 IOHR
I P1[6]
17
Input
XRES iAnctetirvneahl piguhll-edxotewrnn[a2l9]reset with
18 I/O
I P3[0]
19 I/O
I P3[2]
20 I/O
I P4[0]
21 I/O
I P4[2]
22 I/O
I P2[0]
23 I/O
I P2[2] Driven Shield Output (optional)
24 I/O
I P2[4] Driven Shield Output (optional)
25 IOH
I P0[0] Driven Shield Output (optional)
26 IOH
I P0[2] Driven Shield Output (optional)
27 IOH
I P0[4]
28 IOH
I P0[6]
29 Power
30 IOH
I
VDD
P0[7]
31 IOH
I
32 Power
CP Power
P0[3]
VSS
VSS
Integrating input
Ground connection[30]
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
25.
The center pad (CP) on the QFN
it must be electrically floated and
package must be
not connected to
connected to ground
any other signal.
(VSS)
for
best
mechanical,
thermal,
and
electrical
performance.
If
not
connected
to
ground,
26. 28 GPIOs = 25 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
27. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive
resistive
low
low
for
for
512 sleep clock cycles and both the pins transition to
8 sleep clock cycles and transition to high impedance
high impedance state. On reset, after XRES de-asserts,
state. Hence, during power-up or reset event, P1[1] and
the SDA and the SCL
P1[0] may disturb the
lIi2nCesbdusri.vUe se
alternate pins if you encounter issues.
28. Alternate SPI clock.
29. The internal pull down is 5KOhm.
30. All VSS pins should be brought out to one common GND plane.
Document Number: 001-69257 Rev. *O
Page 11 of 45
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY8C20637.PDF ] | |
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